Responsive or non-type flash digital verification method, system, storage medium and terminal

Abstract

The invention discloses a digital verification method and system for a response type NOR flash memory, a storage medium and a terminal. The method comprises the steps of pre-defining exception enabling and corresponding data reliability corresponding to exception data in a data area in a Nor flash memory chip; sending response information to the Nor flash memory chip; and performing correspondingreliability marking on abnormal data of a data area in the Nor flash memory chip according to the response information. Through introduction of positive reliability and negative reliability parameters, on one hand, internal characteristics of an analog circuit are truly reflected, so that the verification process is closer to real behaviors of the memory chip, and on the other hand, internal databits of the memory chip are flexible and controllable, the verification space is larger, and the verification completeness is higher; the use of macro definition is reduced in a simulation model, theintegrity of the simulation model is ensured, and the readability and transportability of the simulation model are improved.

Description

technical field [0001] The invention relates to a verification method, in particular to a response type or non-type flash memory digital verification method, system, storage medium and terminal. Background technique [0002] The digital verification of Nor flash memory chips is different from the verification of SOC chips. The former needs to consider the characteristics of analog circuits, fully extract function points, and reasonably represent and model analog circuits with digital methods, which increases the difficulty of verification. [0003] Taking memory chip wiping logic as an example, the verification methods and means of memory chip logic functions in the industry are introduced. First, a brief description of the rubbing algorithm process is given, such as figure 1 Shown: From the perspective of digital circuits, the erasing operation of the memory chip is the process of changing "0" to "1", and the programming operation of the memory chip is the process of chang...

AI Technical Summary

Problems solved by technology

Obviously, macro definitions and verification use cases should correspond one-to-one. The scope of macro definitions is limited, and each reconstruction of macro definitions will increase the workload. At the same time, the simulation model code has a large number of macro definitions, resulting in low readability and the risk of model errors. Increase, porting to new projects, verification use cases and corresponding macro definition verification intentions need to be reorganized, resulting in greatly reduced portability and increased time costs

[0004] Another common verification method that cannot be judged by the structure is to force read data that is not all "1" when reading the data in the erased area in the verification use case (called a force operation in the industry), so that the judgment cannot be judged. This method avoids adding Macro definition, but the flexibility is lower. When the project is transplanted, due to the change of the internal signal of the simulation model, the use case needs to be re-examined and modified, resulting in low portability. More importantly, the use of a large number of force operations ensures the reliability of the verification results. The degree of confidence is reduced, which greatly increases the verification risk

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