Method and system for reducing erase interference and erase time, storage medium and terminal

A technology of erasing time and over-erasing, applied in the system, a method of reducing erasing interference and erasing time, storage media and terminal fields, can solve the problem of increasing erasing time, to reduce erasing time, The effect of reducing erasure interference and meeting the requirements of product use

Active Publication Date: 2020-10-16
XTX TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The object of the present invention is to provide a method, system, storage medium and terminal for reducing erasing disturbance and erasing time, aiming to solve the problem of increasing Improve the reliability of chip data, but at the same time greatly increase the problem of erasing time

Method used

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  • Method and system for reducing erase interference and erase time, storage medium and terminal
  • Method and system for reducing erase interference and erase time, storage medium and terminal
  • Method and system for reducing erase interference and erase time, storage medium and terminal

Examples

Experimental program
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Embodiment 1

[0080] In said S6, the first refresh process is performed on other programming units in the chip that belong to the same array as the erased unit by sampling inspection:

[0081] s62-1: Randomly extract at least one other storage unit in the chip that belongs to the same array as the erased unit and judge whether the extracted storage unit is an erasing unit or a programming unit. If it is an erasing unit, jump to S7. If it is a programming unit, jump to s62-2;

[0082] s62-2: Refresh and program other memory cells in the chip that belong to the same array as the erased cell, and jump to S7.

[0083] In some specific embodiments, because the randomness is relatively large in the way of random extraction, in order to reduce the reduction of chip reliability caused by randomness, the S6 specifically includes the following steps:

[0084] s62-1: Randomly extract at least one (one or more) other storage units in the chip that belong to the same array as the erased unit and judge ...

Embodiment 2

[0089] In said S6, the first refresh process is performed on other programming units in the chip that belong to the same array as the erased unit in a cyclic manner:

[0090] s63-1: Extract the current storage unit according to the preset extraction arrangement rule and the preset number of storage units and then the last extracted unit, and judge whether the currently extracted storage unit is an erasing unit or a programming unit, if it is an erasing unit Then jump to S7, if it is a programming unit, then jump to s63-2;

[0091] s63-2: Refresh and program the currently extracted memory cells, and jump to S7.

[0092] Among them, the preset extraction arrangement can be in order, for example, the sector numbered 1, the sector numbered 2 and the sector numbered 3 were extracted last time, and the sector numbered 4 is extracted next time. , the sector numbered 5 and the sector numbered 6..., or the sector with an odd number was extracted last time, and the sector with an even ...

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Abstract

The invention discloses a method and a system for reducing erasing interference and erasing time, a storage medium and a terminal. The method comprises the step of performing first refreshing processing on other programming units which belong to the same array as an erased unit in a chip by adopting a sampling inspection mode or performing first refreshing processing on other programming units which belong to the same array as the erased unit in the chip by adopting a circulating mode. Although certain reliability of the chip is sacrificed, the erasing time is greatly reduced, and the use requirements of products are met.

Description

technical field [0001] The present invention relates to the technical field of semiconductor storage, in particular to a method, system, storage medium and terminal for reducing erasing interference and erasing time. Background technique [0002] In memory, under normal circumstances, the size of a sector is 4096 bytes, and the size of a block is 65536 bytes. For a chip with a capacity of 128Mbit, it contains 256 blocks. Usually we put some blocks in the same array, such as Put 32 blocks in an array, memory cells in an array, their substrates are connected together. The following takes a chip with a capacity of 128Mbit as an example, and the size of an array is 16Mbit, that is, 32 blocks are located in the same array, and 512 sectors are located in the same array. [0003] When the sector of the chip is erased, for the array where the sector is located, if there are programming units in other sectors of the array, since the substrates of the entire array are connected toget...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/34G11C16/14
CPCG11C16/14G11C16/345
Inventor 刘梦
Owner XTX TECH INC
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