Original bit error rate reduction method for three-dimensional flash memory

Abstract

The invention discloses an original bit error rate reduction method for a three-dimensional flash memory. The three-dimensional flash memory has large storage capacity and high unit storage density, but the original bit error rate is continuously increased along with long-time storage of data and continuous abrasion of a storage unit. The high original bit error rate reduces the data storage reliability on one hand, and increases the pressure of error correction codes on the other hand, thereby improving the decoding delay, and reducing the performance of a three-dimensional flash memory storage system. The invention provides the original bit error rate reduction method in order to improve three-dimensional flash memory performance and data reliability. The method comprises the following steps: firstly, testing a three-dimensional flash memory chip by utilizing a hardware test platform, counting a transfer proportion between every two adjacent states, and then dynamically adjusting a read voltage between the two adjacent states with a relatively high transfer proportion so as to reduce a high original bit error rate caused by the high transfer proportion, improve the reliability and reduce the delay of an error correction code.

Description

Technical field [0001] The invention belongs to the technical field of solid-state disk storage, and more specifically, relates to a method for reducing the original bit error rate of a three-dimensional flash memory. Background technique [0002] Three-dimensional flash memory has large storage capacity and high cell storage density, mainly due to the use of a three-dimensional hierarchical structure and each cell can store multiple bits of information. However, data reliability has become a major problem, due to the influence of inter-layer interference, preservation, and programmable erasing and writing cycles, resulting in a higher original bit error rate. [0003] The high original error rate reduces the reliability of data storage on the one hand, and on the other hand increases the pressure of error correction codes, increases the decoding delay, and reduces the performance of the 3D flash memory system. For example, for Low Density Parity Check (LDPC), a high original bit ...

AI Technical Summary

Problems solved by technology

Dynamically adjust the read voltage according to the state transition ratio, which can not only effectively reduce the problem of high bit error rate caused by high state transition ratio, but also reduce unnecessary voltage shift operations, thus solving the technical problem of high delay caused by the original bit error rate

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