Original bit error rate reduction method for three-dimensional flash memory

A technology of original bit error rate and flash memory, which is applied in information storage, static memory, read-only memory, etc., and can solve problems such as high delay

Inactive Publication Date: 2020-10-30
上海威固信息技术股份有限公司
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  • Claims
  • Application Information

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Problems solved by technology

Dynamically adjust the read voltage according to the state transition ratio, which can not only effectively reduce the problem of high bit error rate caused by high state transition ratio, but also reduce unnecessary voltage shift operations, thus solving the technical problem of high delay caused by the original bit error rate

Method used

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  • Original bit error rate reduction method for three-dimensional flash memory
  • Original bit error rate reduction method for three-dimensional flash memory

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Embodiment Construction

[0030] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the following further describes the present invention in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0031] The design structure diagram of the present invention is as figure 1 As shown, for three-dimensional MLC (Multi-Level Cell) flash memory, each cell stores two bits of information, and has four storage states, namely state 11, state 10, state 00 and state 01, where the left bit is called the highest The most significant bit (Most Significant Bit, MSB), the right bit is called the Least Significant...

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Abstract

The invention discloses an original bit error rate reduction method for a three-dimensional flash memory. The three-dimensional flash memory has large storage capacity and high unit storage density, but the original bit error rate is continuously increased along with long-time storage of data and continuous abrasion of a storage unit. The high original bit error rate reduces the data storage reliability on one hand, and increases the pressure of error correction codes on the other hand, thereby improving the decoding delay, and reducing the performance of a three-dimensional flash memory storage system. The invention provides the original bit error rate reduction method in order to improve three-dimensional flash memory performance and data reliability. The method comprises the following steps: firstly, testing a three-dimensional flash memory chip by utilizing a hardware test platform, counting a transfer proportion between every two adjacent states, and then dynamically adjusting a read voltage between the two adjacent states with a relatively high transfer proportion so as to reduce a high original bit error rate caused by the high transfer proportion, improve the reliability and reduce the delay of an error correction code.

Description

Technical field [0001] The invention belongs to the technical field of solid-state disk storage, and more specifically, relates to a method for reducing the original bit error rate of a three-dimensional flash memory. Background technique [0002] Three-dimensional flash memory has large storage capacity and high cell storage density, mainly due to the use of a three-dimensional hierarchical structure and each cell can store multiple bits of information. However, data reliability has become a major problem, due to the influence of inter-layer interference, preservation, and programmable erasing and writing cycles, resulting in a higher original bit error rate. [0003] The high original error rate reduces the reliability of data storage on the one hand, and on the other hand increases the pressure of error correction codes, increases the decoding delay, and reduces the performance of the 3D flash memory system. For example, for Low Density Parity Check (LDPC), a high original bit ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/08G11C16/26G11C16/30G11C29/42
CPCG11C16/08G11C16/26G11C16/30G11C29/42
Inventor 刘碧贞苗诗君余云李礼吴佳
Owner 上海威固信息技术股份有限公司
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