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Manufacturing method of self-aligned quadruple graph

A manufacturing method and self-alignment technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of high cost and complex overall process, and achieve the effect of saving process cost and reducing process steps

Pending Publication Date: 2020-10-30
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The existing method of removing the first sidewall layer adds SOC backfilling, etchin

Method used

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  • Manufacturing method of self-aligned quadruple graph
  • Manufacturing method of self-aligned quadruple graph
  • Manufacturing method of self-aligned quadruple graph

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Experimental program
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Embodiment Construction

[0039] In order to make the purpose, technical solution and advantages of the present invention clearer, the specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0040] as attached figure 1 As shown, a method for making a self-aligned quadruple pattern provided by the present invention comprises the following steps:

[0041] S01: as attached figure 2 As shown, the second mandrel layer 2, the mask dielectric layer 3, the first mandrel layer 4 and the photoresist layer are sequentially deposited on the substrate 1; and the photoresist layer is patterned to define the photolithography after patterning The layers have a first pitch.

[0042] The substrate can be but not limited to a silicon nitride substrate; the second mandrel layer and the first mandrel layer can be but not limited to an amorphous silicon layer, wherein the thickness of the second mandrel layer can be 500-900 angstr...

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PUM

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Abstract

The invention discloses a manufacturing method of a self-aligned quadruple graph. The method comprises the steps of depositing a second side wall layer on a second mandrel mask layer and a mask dielectric layer at the same time, etching in the same inductively coupled plasma reaction cavity to remove the second side wall layer, a second mandrel mask layer and a mask dielectric layer in the horizontal direction and combining the removal of the mask dielectric layer and the removal of the second mandrel mask layer together for processing. So, the process of removing a first side wall layer and the mask dielectric layer by adopting an SOC reverse filling mode in the prior art is avoided, the process steps are reduced, and the process cost is saved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for making a self-aligned quadruple pattern. Background technique [0002] With the continuous shrinking of the chip size, after entering the FinFET (Fin Field-Effect Transistor, Fin Field Effect Transistor) technology era, especially starting from the 7nm node, due to the graphics cycle (such as the node corresponding to the fin (Fin) of the 7nm node The pitch (30nm) has exceeded the exposure limit of the 193nm immersion lithography machine, so the self-aligned quadruple imaging technology (Self-Aligned Quadruple Patterning, SAQP) is introduced to define graphics; such as fin graphics or back-end metal layer graphics. [0003] After the traditional SAQP technology forms the first side wall layer, when transferring graphics from the first side wall layer to the second mandrel layer, it will encounter the problem of removing the first side wall layer, that is, ...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L29/78
CPCH01L29/6656H01L29/66795H01L29/785
Inventor 杨渝书王伯文伍强李艳丽
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT