Method and system for optimizing power consumption of digital circuit and storage medium

Abstract

One embodiment of the invention provides a layer digital circuit power consumption optimization method and system, and a storage medium, and the method comprises the steps: building time sequence violation restoration; according to the time sequence violation repair, establishing a time sequence repair program; according to the time sequence violation repair, screening and deleting a removable buffer through the time repair program; repairing the retention time violation, and completing the power consumption optimization of the digital circuit. According to the method, different process sequences are mainly utilized, and the purpose of better optimizing power consumption is achieved by changing the sequence of time sequence repair and power consumption optimization. Because the power consumption optimization method is to reduce the size of the device or reduce the number of buffers, and the reduced size of the device is actually beneficial to the power consumption and the retention time, the maintenance time is put after the power consumption optimization, so the use amount of the device can be reduced when the maintenance time is shortened, and the optimization of the area and thepower consumption is further facilitated.

Description

technical field [0001] The invention relates to the technical field of digital circuit design, in particular to a method, system and storage medium for optimizing power consumption of a digital circuit. Background technique [0002] With the rapid development of technology and technology, power consumption has become a very critical issue in integrated circuit design. After entering the deep submicron and nanometer technology, the size of the device is further reduced, the performance of the circuit is improved rapidly, and the integration of the circuit is increased rapidly. A lot of new power consumption problems have been solved, for example, the rapid increase of leakage current has caused a series of new problems. Low-power design also faces more problems and higher requirements, especially in applications that are sensitive to power consumption increases, such as high-performance computer systems, portable electronic products, and mobile communication products. [000...

AI Technical Summary

Problems solved by technology

[0003] In the implementation process of digital circuits, the traditional power consumption optimization process is to optimize the power consumption after the timing is completely converged. Although this method can reduce the power consumption of the chip to a certain extent, it is necessary to repair and maintain the chip when the timing of the chip is converged. The increased chip area of ​​the timing violation is wasted

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