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Host cpu architecture system and method for safely managing hardware resources

A hardware resource and safety management technology, applied in the field of host CPU architecture system, can solve problems such as hidden safety hazards, and achieve the effect of improving safety

Active Publication Date: 2021-07-16
HYGON INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This could be a security risk

Method used

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  • Host cpu architecture system and method for safely managing hardware resources
  • Host cpu architecture system and method for safely managing hardware resources
  • Host cpu architecture system and method for safely managing hardware resources

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Embodiment Construction

[0025] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. The same or similar components may be denoted by similar reference numerals even though they are shown in different drawings. Detailed descriptions of constructions or processes known in the art may be omitted to avoid obscuring the subject matter of the present disclosure.

[0026] Host CPU architecture system

[0027] figure 1 A block diagram of a conventional CPU architecture system 100 for managing hardware resources is shown.

[0028] If a trusted proprietary kernel program is used to process the MMU / CR3, in order to exclude access to specific hardware resources by untrusted programs, additional binary file scanning overhead is introduced, resulting in process switching delays and affecting overall system performance; The trusted kernel program and the host operating system kernel work at the same privilege level and share the CPU address space, so ...

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Abstract

A system and method for securely managing hardware resources in a host CPU architecture system are provided, the system includes a host CPU and a security processor, wherein the security processor is different from and separated from the host CPU, and the security processor controls processes related to physical memory page management specific registers, and the security processor is configured to: in response to an operation request sent by the host CPU for a specific register related to physical memory page management, based on the type of the specific register, deny the host CPU’s operation request or only allow the host CPU to read Fetch a specific register.

Description

technical field [0001] The invention relates to processor technology, in particular to a host CPU architecture system and method for safely managing hardware resources. Background technique [0002] Most of the existing commercial operating systems are designed based on the macro kernel. All processes share the same kernel space. The kernel has the highest privilege level of the central processing unit (CPU), and manages all hardware resources and process page tables at the same time. information and contextual information. This can be a security risk. Contents of the invention [0003] technical problem [0004] At present, most operating system kernels have the highest CPU privilege level and directly manage the page table of the process, including the creation of the page table and the update of the CR3 register. Malicious codes can gain sufficient privileges to access all kernel data and hardware resources by exploiting operating system kernel vulnerabilities, reduc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F21/57
CPCG06F21/57
Inventor 姜新应志伟刘子行
Owner HYGON INFORMATION TECH CO LTD