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Manufacturing method of three-dimensional memory

A manufacturing method and memory technology, which are applied to electric solid-state devices, semiconductor devices, electrical components, etc., can solve problems such as inaccurate positioning, damage to the ON layer in the step area, and development residues, so as to avoid recess defects, protect three-dimensional structures, reduce The effect of photoresist amount

Active Publication Date: 2020-11-20
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, in the process of planarizing the core area to eliminate the height difference, the greater the height difference between the core storage array area and the step area, the more dielectric material and photoresist material will be consumed, and too much photoresist will lead to development residue, positioning Inaccurate and damage to the ON layer in the step area

Method used

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  • Manufacturing method of three-dimensional memory
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  • Manufacturing method of three-dimensional memory

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Embodiment Construction

[0023] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0024] In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways than those described here, so the present invention is not limited by the specific embodiments disclosed below.

[0025] As indicated in this application and claims, the terms "a", "an", "an" and / or "the" do not refer to the singular and may include the plural unless the context clearly indicates an exception. Generally speaking, the terms "comprising" and "comprising" only suggest the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list, and the method or device may also contain other st...

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Abstract

The invention relates to a manufacturing method of a three-dimensional memory, which comprises the following steps of: providing a semiconductor structure which is provided with a substrate and a stacking structure formed on the substrate, wherein the stacking structure comprises a core storage region and a step region; covering a dielectric layer above the core storage region and the step region;covering a first photoresist layer above the dielectric layer above the step region; exposing the first photoresist layer to form a super-crosslinked structure layer; covering a second photoresist layer above the super-crosslinked structure layer; removing the dielectric layer above the core storage region; and removing the second photoresist layer and the super-crosslinking structure layer abovethe step region. According to the manufacturing method, the use amount of light resistance in the core region planarization process can be reduced, the three-dimensional structures of the step regionand the core storage region can be effectively protected, and the defect of recession is avoided.

Description

technical field [0001] The invention relates to the field of manufacturing integrated circuits, in particular to a method for manufacturing a three-dimensional memory. Background technique [0002] In order to overcome the limitations of two-dimensional memory devices, memory devices with a three-dimensional (3D) structure have been developed and mass-produced in the industry, which improves integration density by three-dimensionally arranging memory cells on a substrate. [0003] As the number of 3D NAND layers continues to increase, the number of oxide-nitride (ON) layers in the three-dimensional memory structure continues to increase, and the step heights also continue to increase. After the step process is formed, there is a certain height difference between the core storage array area and the step area. In order to facilitate subsequent processes, it is necessary to eliminate the height difference, such as introducing a dielectric layer, and by etching and chemical mech...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11524H01L27/11551H01L27/1157H01L27/11578H10B41/35H10B41/20H10B43/20H10B43/35
CPCH10B41/35H10B41/20H10B43/35H10B43/20
Inventor 刘云飞
Owner YANGTZE MEMORY TECH CO LTD