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Board-level debugging method without JTAG intervention

A debugging method and board-level technology, applied in the electronic field, can solve problems such as inability to debug, difficulty in debugging board-level codes, and demanding processor platforms

Active Publication Date: 2020-11-24
RES INST OF PHYSICAL & CHEM ENG OF NUCLEAR IND
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But when the target chip does not provide a JTAG interface, it becomes very difficult to debug board-level code
Some modern operating systems provide board-level debugging by providing special debugging tools such as GDB, but they have strict requirements on the processor platform (with MMU, the code must run in RAM), and cannot be debugged in a bare-metal environment without an operating system

Method used

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  • Board-level debugging method without JTAG intervention
  • Board-level debugging method without JTAG intervention
  • Board-level debugging method without JTAG intervention

Examples

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specific Embodiment approach

[0082] Specific implementation methods: a board-level debugging method without JTAG intervention, and its program is bundled with the target application and downloaded to the target circuit board. When the target processor starts to run the program, the debugging software starts to run first, and its software structure is as follows: figure 1 shown. It first initializes its own environment, and then according to image 3 or Figure 4 The hardware configuration of the single-step simulation registers the interrupt interface of the analog part to the corresponding interrupt vector of the processor, and initializes the communication peripherals. Then turn to the debugging state management part to run. The debugging state management part calls the interface of the external communication management logic to obtain the debugging behavior expected by the user, read and write specific memory, monitor memory variables or add / delete program breakpoints according to the debugging behav...

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Abstract

The invention discloses a JTAG (Joint Test Action Group) intervention-free board-level debugging method, which comprises the following steps of: 1) binding debugging software and target software for downloading or respectively downloading the debugging software and the target software and realizing the running of the debugging software and the target software; and 2) interrupt execution and control of debugging software on debugged software are realized by processor peripheral interrupt or external board-level interrupt. According to the board-level debugging method, the traditional JTAG function is simulated by using independent debugging software bound with target software through peripheral equipment and external interruption intervention, and the board-level debugging method which doesnot limit a processor platform, supports a bare computer environment without an operating system and does not need JTAG intervention is realized.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to a board-level debugging method without JTAG intervention. Background technique [0002] In the embedded system software development process, using hardware JTAG to debug is an important debugging method. But when the target chip does not provide a JTAG interface, it will become very difficult to debug the board-level code. Some modern operating systems provide board-level debugging by providing special debugging tools such as GDB, but they have strict requirements on the processor platform (with MMU, the code must run in RAM), and cannot be debugged in a bare-metal environment without an operating system. Contents of the invention [0003] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a board-level debugging method without JTAG intervention, which supports a bare-metal environment without an operating system a...

Claims

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Application Information

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IPC IPC(8): G06F11/36
CPCG06F11/3652
Inventor 赵楠
Owner RES INST OF PHYSICAL & CHEM ENG OF NUCLEAR IND