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FPGA engineering test method of federated learning system

A test method and federated technology, applied in the field of FPGA engineering testing, can solve problems such as difficult external judgment of FPGA working status, difficult fault location, complex structure, etc.

Pending Publication Date: 2020-11-27
CLUSTAR TECH LO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] When performing engineering tests on FPGA, such as directly testing the complete functions of FPGA, since there are many calculation modules and control modules in the FPGA project of the federated learning system, the structure is complex, and there are many test points for direct testing. , it is difficult to judge the working status of the FPGA from the outside, and it is difficult to locate the fault

Method used

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  • FPGA engineering test method of federated learning system
  • FPGA engineering test method of federated learning system
  • FPGA engineering test method of federated learning system

Examples

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Embodiment Construction

[0020] The subject matter described herein will now be discussed with reference to example implementations. It should be understood that these embodiments are discussed only to enable those skilled in the art to better understand and implement the subject matter described herein, and not to limit the scope of protection, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements discussed without departing from the scope of the description. Various examples may omit, substitute, or add various procedures or components as desired. For example, the methods described may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with respect to some examples may also be combined in other examples.

[0021] As used herein, the term "including" and variations thereof represent open-ended terms meaning "including but not limited to". The ter...

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Abstract

The embodiment of the invention provides an FPGA engineering test method. An FPGA is applied to a heterogeneous processing system for federated learning, the heterogeneous processing system comprisesan upper computer and the FPGA, the test method comprises the steps that the upper computer sends configuration data and test source data to the FPGA, and the configuration data comprises specified test configuration data; and the FPGA receives the test source data and processes the test source data in a specified test module according to the configuration data to obtain test result data. Throughthe FPGA engineering test mode, the specified test module of the FPGA can be tested, and once an abnormality occurs, the abnormality of the specified test module of the FPGA can be directly positioned, so that the troubleshooting range is narrowed and the FPGA engineering test efficiency is improved in comparison with direct engineering test on the whole module.

Description

technical field [0001] The embodiments of this specification generally relate to the field of federated learning, and in particular, relate to an FPGA engineering testing method used in a federated learning system. Background technique [0002] Federated learning is a system based on distributed learning, which disperses the calculation of machine learning to the databases of participating parties for encrypted distributed computing. In order to coordinate each distributed computing node, the gradient-related data needs to be transmitted, which requires privacy protection for the gradient-related data, and the complexity of the related algorithm is relatively high. The federated learning system has a huge demand for computing performance, and field programmable gate array FPGA (Field Programmable Gate Array) provides powerful computing performance for federated learning. [0003] When performing engineering tests on FPGA, such as directly testing the complete functions of F...

Claims

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Application Information

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IPC IPC(8): G06F11/22G06N20/00
CPCG06F11/2247G06F11/2273G06N20/00
Inventor 程孝典王玮胡水海
Owner CLUSTAR TECH LO LTD