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Cache arrangement for graphics processing systems

A graphics processing and graphics processor technology, applied in image data processing, processor architecture/configuration, memory system, etc., can solve the problem of large memory bandwidth consumed by graphics processing operations

Pending Publication Date: 2020-12-04
ARM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] As GPUs get larger (and graphics content more complex), graphics processing operations consume greater and greater memory bandwidth

Method used

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  • Cache arrangement for graphics processing systems
  • Cache arrangement for graphics processing systems
  • Cache arrangement for graphics processing systems

Examples

Experimental program
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Embodiment Construction

[0132] This embodiment relates to graphics processing systems using so-called "tile-based" rendering. In tile-based rendering, the two-dimensional scene to be displayed is subdivided or divided into a number of smaller sub-regions, referred to herein as "tiles". The tiles are each rendered individually (usually one after the other), and the rendered tiles are then reassembled to provide a complete frame for display. In such settings, the scene is usually divided into subregions (tiles) of regular size and shape (for example, they are usually square or rectangular), but this is not required.

[0133] In a tile-based rendering system, in a first processing pass, a list of primitives to be rendered (i.e., a "tile list") is thus prepared for each tile, identifying (e.g., by referring to indicator) actually exist in a given tile and need to be rendered for that tile. The process of preparing a tile list for a tile generally involves (with a desired level of accuracy) determining ...

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PUM

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Abstract

The invention relates to a caching device for a graphic processing system, and discloses a graphic processing system. The graphics processing system has a buffer system (24) disposed between a memory(23) and a graphics processor (20). The buffer system comprises a first buffer (53) for transferring data to and from the graphics processor (20) and a second buffer (54) arranged and configured to transfer data between the first buffer (53) and the memory (23). When data is to be written from the first buffer (53) to the memory (23), the buffer controller (55) determines a data type of the data and causes the data to be written into the second buffer (54) without writing the data to the memory (23) depending on the data type; or such that the data is written to the memory (23) without storingthe data in the second buffer (54). In an embodiment, the second buffer (54) is assigned to write only.

Description

technical field [0001] The present invention relates to graphics processing systems, and in particular to caching operations in graphics processing systems. Background technique [0002] Graphics processing is typically performed by first dividing the scene to be displayed into a number of similar elementary components or "primitives" and then performing the desired graphics processing operations on these primitives. Graphics "primitives" typically take the form of simple polygons, such as triangles. [0003] At this stage, individual primitives are defined by and represented as a set of vertices. Each vertex of a primitive is associated with a set of data representing that vertex, such as position, color, texture and other attribute data. This "vertex data" is then used, for example, when rasterizing and rendering the vertex-related primitives to generate the desired rendered output of the graphics processing system. [0004] Thus, when a primitive and its vertices have ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06T1/20G06T1/60
CPCG06T1/20G06T1/60G06F2212/1016G06F2212/455G06F12/0811G06F12/128G06F12/0888G06F12/0875G06T15/005G06F2212/302G06F12/0842G06F2212/608G06F2212/1044G06F12/0831
Inventor O·H·乌尔恩霍特
Owner ARM LTD