DFT circuit construction method in integrated circuit test mode and application

Abstract

The invention discloses a DFT circuit construction method in an integrated circuit test mode and an application thereof, and the method comprises the steps: S1, obtaining the function clock information in an integrated circuit, and carrying out the grouping according to the logic interaction relation between function clocks, wherein a logic interaction relationship does not exist between any two functional clocks divided into the same clock group; S2, setting global DFT clocks with the same number as the clock groups, enabling the global DFT clocks to be in one-to-one correspondence with the clock groups, and enabling the global DFT clocks to take over all function clocks in the corresponding clock groups; and S3, for each clock group, linking the functional clocks in the clock group to the same scan chain to complete the scan chain circuit construction of the clock group. The method has the advantages of improving an integrated circuit test mode time sequence, avoiding insertion of alarge number of buffer units and the like.

Description

technical field [0001] The present invention relates to the field of integrated circuit testability design (Design for Test, DFT), in particular to a DFT circuit construction method and application in an integrated circuit test mode, including a DFT circuit construction system, a storage medium and a device. Background technique [0002] With the progress of the integrated circuit manufacturing process, the complexity of the chip is increasing, and how to design the circuit for testability of the chip is becoming more and more challenging. The key to design for testability is controllability and observability. Controllability is the ability to set and reset each node inside the circuit. Observability is the ability to directly or indirectly observe the state of any node in the circuit. The purpose of design for testability is twofold: first, to find out the fixed faults of the chip, such as the disconnection of the test chain circuit caused by the manufacturing process; seco...

AI Technical Summary

Problems solved by technology

However, because the traditional design for test method divides the two clocks with logical paths in the functional mode into a DFT clock group, and then chains the registers according to the DFT clock group, resulting in

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