Floating point exception processing method and device

An exception handling and floating-point technology, applied in the computer field, can solve problems such as slow precision, and achieve the effect of improving computing performance, improving computing efficiency, computing time and circuit area.

Pending Publication Date: 2021-01-12
VIA ALLIANCE SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Denormalized numbers are progressively underflowed because a slow (gradual) loss of precision is allowed when the result is small

Method used

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  • Floating point exception processing method and device
  • Floating point exception processing method and device
  • Floating point exception processing method and device

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0241] Example 1 (operand A and operand B are both normalized numbers)

[0242] LZC A = 0, LZC B =0, no need to go through LZC at this time, if normalization is detected, set LZC directly A = 0, LZC B =0.

[0243] Assume that operand A is 1.25, and operand B is 2.345, assuming that the operands are all single-precision floating-point numbers. The following is an example of the step-by-step evolution of each operand in the operation process in the form of a table.

[0244] Operand A: 0x3FA0000 (ie decimal 1.25)

[0245]

[0246] Operand B: 0x4016147B (ie decimal 2.345)

[0247]

[0248] In the implementation process, not all channels need to be extended to 64-bit, which means that the input operands of some channels can be expanded in bit width.

[0249] Note that in this example, the LZC of the input operands are all 0.

[0250] First Exponent Result = ExpA – LZC A +ExpB–LZC B +Bias sp

[0251] =(17’hFFFF-17’hFFFF)–0+(17’h10000-17’hFFFF)–0+8’7F

[0252] =8'h1...

example 2

[0262] Example 2 (operand A is a normalized number, and operand B is a denormalized number)

[0263] Such as Figure 9 As shown, the calculation obtains the first exponent result Exp and the first mantissa result.

[0264] If the result of the first index is smaller than the minimum exponent, it indicates an underflow. At this time, it is necessary to calculate the difference between the result of the first index and the minimum exponent to determine the actual mantissa shift (Underflow shift counter). The algorithm is as follows:

[0265] Underflow shift counter=MinExp–Exp=MinExp+~Exp+1;

[0266] If(Underflow shift counter>64)

[0267] Underflow shift counter = 64;

[0268] Else Underflow=MinExp+~Exp+1.

[0269] Denormalized example

[0270] Operand A: 0x3F7FFFFF

[0271]

[0272] Operand B: 0x00000001

[0273]

[0274] In decimal, theoretically the exponential result in the operation result = ExpA–LZC A +(ExpB–LZC B )+Bias sp=(-1)-0+(-127-22)+127=-23<0 to judg...

example 3

[0358] Example 3 (operand A and operand B are both normalized numbers)

[0359] Operand A: 0x3E80000 (ie decimal 0.25)

[0360]

[0361] Operand B: 0x3F00000 (ie decimal 0.5)

[0362]

[0363] Exponential subtraction:

[0364] The third exponent result = (ExpA – LZC A )–(ExpB-LZC B )+Bias SP

[0365] =(17’hFFFD–17’hFFFF-0)–(17’FFFE-17’hFFFF-0)+8’h7F

[0366] =8'h7E>8'h0. Therefore, the third index result did not underflow.

[0367] Third mantissa result:

[0368] Mantissa A / Mantissa B=

[0369] 64'h8000000000000000 / 64'h8000000000000000

[0370] =64'h8000000000000000

[0371] mantissa shift bit = 0

[0372] Final mantissa result = 24'h800000

[0373] Second division result:

[0374] sign[31] Exponent[30:23] Imp. Mantissa[22:0] 0 01111110 1 00000000000000000000000

[0375] Second division result = 0x3f000000 (ie decimal 0.5)

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PUM

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Abstract

The invention relates to a floating point exception processing method and device. The floating point exception handling method comprises the following steps: if floating point exception is detected toexist in operands of floating point operation, correcting the operands according to the number of leading zeros in the process of performing the floating point operation on the operands by adopting an arithmetic unit corresponding to the operation type of the floating point operation to obtain an operation result; if it is detected that the operand does not have the floating point exception, directly adopting an arithmetic unit corresponding to the operation type of the floating point operation to carry out the floating point operation on the operand to obtain an operation result; if the operation result overflows downwards, correcting the operation result. According to the floating point exception processing method and device, repeated execution of the cyclic repair process is prevented,complex interaction among multiple modules is not needed, different processing flows and modes are set according to whether floating point exception exists in operands or not, the processing flexibility is improved, and therefore the operation efficiency is improved.

Description

technical field [0001] The present disclosure relates to the field of computer technology, in particular to a method and device for processing floating-point exceptions. Background technique [0002] The IEEE (Institute of Electrical and Electronics Engineering) Standard (IEEE 754) for floating-point arithmetic specifies how to represent floating-point numbers of single precision, double precision, single extended precision, and double extended precision. [0003] IEEE 754 standard uses V=(-1) s *M*2 E The form approximates a number. and divides the bit representation of the floating-point number into three fields: [0004] The sign (sign) s field determines whether the number is a negative number or a positive number, wherein s=0 indicates a positive number, and s=1 indicates a negative number. [0005] Mantissa (significand, also known as mantissa, hereinafter referred to as man) M is a binary decimal, its range is 1 ~ 2-ξ or 0 ~ 1-ξ, mantissa field M uses n-bit decima...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/499
CPCG06F7/49915
Inventor 袁苗苗张稚
Owner VIA ALLIANCE SEMICON CO LTD
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