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Anti-fuse one-time programmable memory cell

一种存储单元、反熔丝的技术，应用在电气元件、晶体管、电固体器件等方向，能够解决多硅面积、占用等问题

Active Publication Date: 2021-01-15
ZHUHAI CHUANGFEIXIN TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, transistors with high-voltage junctions will take up more silicon area due to the need for wider channel lengths and widths, and more silicon area will directly correlate to higher cost

Method used

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  • Anti-fuse one-time programmable memory cell
  • Anti-fuse one-time programmable memory cell
  • Anti-fuse one-time programmable memory cell

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0021] In the embodiments of the present invention, the technical solutions in the embodiments of the present invention are described with reference to the accompanying drawings.

[0022] In some embodiments, the antifuse otp memory uses metal oxide semiconductor (mos) capacitors as antifuse elements. The Mos capacitor is connected to an access device called a select transistor, usually a metal-oxide-semiconductor field-effect transistor (mosfet), to form a one-transistor-capacitor (1t1c) antifuse memory bitcell. refer to Figure 1a-1c , one transistor one capacitor (1t1c)) antifuse otp memory cell 100 includes select transistor 110 and antifuse capacitor 120, select transistor 110 includes gate 115 on gate dielectric 116 on substrate 105, antifuse capacitor 120 includes a gate 125 on a gate dielectric 126 on the substrate 105) formed by lightly doped regions 111, 112 and deeply doped regions 113, 114, respectively, the junction of the antifuse capacitor 120 (such as the sour...

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PUM

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Abstract

An anti-fuse one-time programmable memory cell includes a substrate, a select transistor formed on the substrate, and an antifuse capacitor formed on the substrate. The select transistor includes a first gate dielectric layer formed on the substrate, a first gate formed on the gate dielectric layer, a first low voltage junction formed in the substrate, and a second low voltage junction formed in the substrate. A source and a drain of the select transistor are formed of a first low voltage junction and a second low voltage junction. The anti-fuse capacitor includes a second gate dielectric layer formed on the substrate, a second gate formed on the gate dielectric layer, a third low voltage junction formed in the substrate, and a fourth low voltage junction formed in the substrate. The source electrode and the drain electrode of the anti-fuse capacitor are respectively formed by a third low-voltage junction and a fourth low-voltage junction.

Description

[0001] This application is required to be submitted to the United States Patent Office on January 15, 2020, the application number is 16744060, and the title of the invention is "Anovel antifuse OTP structure with hybrid device and hybrid junction for select transistor A novel antifuse OTP with a hybrid device and a selection transistor with a hybrid junction structure", the entire contents of which are incorporated herein by reference. technical field [0002] The invention relates to the technical field of semiconductor memory, in particular to a one-time programmable otp memory. Background technique [0003] Embedded non-volatile memory (envm) technology has been used in many applications such as post-silicon tuning, memory repair, in-circuit field testing and secure id storage. Envm is also a key component for self-healing applications, where information about time-dependent failure mechanisms such as circuit aging must be preserved during system power down cycles. Anti...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/112
CPCH10B20/20H01L23/5252
Inventor 李立王志刚
Owner ZHUHAI CHUANGFEIXIN TECH CO LTD