Three-dimensional memory and its manufacturing method
A manufacturing method and memory technology, applied in the direction of semiconductor devices, electric solid state devices, electrical components, etc., can solve the problems of large space, limit the size of CMOS wafers, reduce the flexibility of back-end wiring, etc., and achieve size reduction and increase The effect of high utilization
Active Publication Date: 2022-04-15
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
The capacitor structure occupies a relatively large space on the CMOS wafer, which limits the further reduction of the size of the CMOS wafer and the flexibility of the back-end wiring.
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[0050] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present invention.
[0051] In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Orientation indicated by rear, left, right, vertical, horizontal, top, bottom, inside, outside, clockwise, counterclockwise, etc. The positional relationship is based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the pr...
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The invention relates to the field of semiconductor devices, and discloses a three-dimensional memory and a manufacturing method thereof. The three-dimensional memory includes: a substrate, including a first area, and a second area around the first area; an array structure, located above the first area of the substrate; a capacitor structure, located in the second area, and includes: a dielectric layer , located on the second region of the substrate; the first electrode layer, located on a part of the dielectric layer; the insulating layer, located on the first electrode layer; the first conductive structure, extending vertically on the insulating layer, and in phase with the first electrode layer Contact: the second conductive structure extends vertically to the insulating layer and the dielectric layer, is located on the periphery of the first electrode layer, and is in contact with the substrate. The three-dimensional memory and its manufacturing method provided by the invention realize the transfer of part of the capacitance structure from the CMOS wafer to the array wafer, which is beneficial to reducing the size of the CMOS wafer.
Description
technical field [0001] The invention relates to the field of semiconductor devices, in particular to a three-dimensional memory and a manufacturing method thereof. Background technique [0002] In recent years, the development of flash memory (Flash Memory) is particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. Has been widely used. In order to further increase the bit density (Bit Density) of the flash memory while reducing the bit cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been developed rapidly. [0003] In the 3D NAND flash memory structure, it includes the memory array structure and the CMOS circuit structure above the memory array structure. The memory array structure and the CMOS circuit structure are usually formed on two different wafers, and then the CMOS circuit is ...
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IPC IPC(8): H01L27/11524H01L27/11529H01L27/11531H01L27/11551H01L27/1157H01L27/11573H01L27/11578
CPCH10B41/35H10B41/41H10B41/42H10B41/20H10B43/35H10B43/40H10B43/20
Inventor 陈亮
Owner YANGTZE MEMORY TECH CO LTD