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Memory element test circuit and memory element test method

A technology for storage components and test circuits, applied in static memory, instruments, etc., can solve problems such as loss of logic values, failure to test memory, etc., and achieve the effect of comprehensive testing

Pending Publication Date: 2021-02-02
REALTEK SEMICON CORP
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the current built-in self-test (BIST) circuit can only be tested in the function mode of the memory, and cannot test whether the memory will be affected after the memory returns to the function mode from the low power consumption mode. low-power mode effect, and loses the logic value it should hold

Method used

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  • Memory element test circuit and memory element test method
  • Memory element test circuit and memory element test method
  • Memory element test circuit and memory element test method

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Embodiment Construction

[0012] The technical terms in the following explanations refer to the customary terms in this technical field. If some terms are explained or defined in this manual, the explanations of these terms shall be based on the descriptions or definitions in this manual.

[0013] The disclosed content of the present invention includes a memory element test circuit and a memory element test method. Since some of the components included in the storage element testing circuit of the present invention may be known components individually, the details of the known components will be described below without affecting the full disclosure and implementability of the device invention. Abridged. In addition, part or all of the process of the storage element testing method of the present invention may be in the form of software and / or firmware, and may be executed by the storage element testing circuit of the present invention or its equivalent device, without affecting the full scope of the met...

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Abstract

The invention discloses a storage element test circuit and a storage element test method. The storage element testing circuit is used for testing a storage element and comprises a storage circuit, a comparison circuit and a control circuit. The storage circuit stores test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled with the storage circuit, the comparison circuit and the storage element and used for executing the following steps to test the storage element: writing the test data into the storage element; controlling the storage element to enter a low power consumption mode; controlling the storage element to enter a function mode; and controlling the comparison circuit to compare output data of the storage element with the test data.

Description

technical field [0001] The invention relates to a memory element, in particular to a test circuit and a test method of the memory element. Background technique [0002] In order to reduce the standby power consumption of the System on a Chip (SoC) and maintain the stored value of the storage element, the circuit usually adds a low power mode for control. Taking the memory application as an example, the low power consumption mode of the memory includes a light sleep mode and a deep sleep mode. However, the current built-in self-test (BIST) circuit can only be tested in the function mode of the memory, and cannot test whether the memory will be affected after the memory returns to the function mode from the low power consumption mode. affected by low-power mode, and loses the logic value it should hold. Therefore, there is a need for a built-in self-test circuit capable of testing the low power consumption mode of the memory. Contents of the invention [0003] In view of ...

Claims

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Application Information

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IPC IPC(8): G11C29/12
CPCG11C29/12
Inventor 林盛霖林士杰
Owner REALTEK SEMICON CORP
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