Semiconductor device

Abstract

The invention discloses a semiconductor device. The semiconductor device includes: a memory array structure including a plurality of memory strings, a plurality of local bit lines, and a plurality ofglobal bit lines, and a peripheral structure located on the memory array structure and comprises a plurality of local bit line selection modules and at least one global bit line selection module, wherein each local bit line is correspondingly connected with at least one memory string, the output end of each local bit line selection module is correspondingly connected with a plurality of local bitlines through a first through hole, the input end of each local bit line selection module is correspondingly connected with a global bit line through a second through hole, and the output end of eachglobal bit line selection module is correspondingly connected with the plurality of global bit lines through a third through hole. According to the invention, the wiring path of the global bit lines can be simplified, and the load of the global bit lines is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device. Background technique [0002] Semiconductor devices (such as three-dimensional memory) are generally formed by bonding array wafers and CMOS (Complementary Metal Oxide Semiconductor) wafers. In the prior art, the array wafer includes a plurality of memory strings and local bit lines (local bit line, LBL), and the CMOS wafer includes global bit lines (global bit line, GBL) and a multiplexer, and the multiplexer passes The global bit line and the local bit line select corresponding memory strings and apply signals. [0003] However, since both the global bit lines and the multiplexer are located in the CMOS wafer, the routing channel in the CMOS wafer is complicated, which in turn results in a high load on the global bit lines. Contents of the invention [0004] The invention provides a semiconductor device, which can simplify the wiring path of t...

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Problems solved by technology

[0003] However, since both the global bit line and the multiplexer are located in the CMOS wafer, the routing channel in the CMOS wafer is complicated, which in turn leads to a high load on the global bit line.

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