JTAG data capture and analysis system

Abstract

A JTAG data capture and analysis system comprises a JTAG communication signal acquisition sub-module, a communication signal analysis and communication protocol analysis sub-module and a user interaction sub-module. The JTAG communication signal acquisition sub-module acquires a JTAG communication signal between a target processor and a simulator through an ADC. The communication signal analysis and communication protocol analysis sub-module diagnoses a communication fault existing between the target processor and the simulator by analyzing the waveform of each signal in a JTAG debugging interface and communication data of a higher layer, and determines a fault source between two communication parties. The user interaction sub-module displays the wrong communication signal and the failed communication protocol and gives a fault diagnosis result. The fault source in JTAG communication is diagnosed by analyzing the communication protocol of the JTAG debugging interface, so that the debugging efficiency of the processor is improved.

Description

technical field [0001] The invention belongs to the technical field of computer system debugging, in particular to a JTAG data capture and analysis system. Background technique [0002] Computer processors typically debug / emulate and download programs via JTAG. In the FPGA verification stage, sample test stage and user board-level design stage, the processor needs to establish normal communication between the emulator and the target processor through JTAG, and then the subsequent hardware debugging simulation and program download can be performed, such as figure 1 shown. The normal operation of the JTAG communication circuit is the basis for the subsequent debugging of the processor chip. However, traditional debugging methods such as oscilloscopes have problems such as slow debugging efficiency and high reliance on hardware engineer debugging experience. [0003] Computer processor JTAG circuit logic design errors, emulator signal distortion, JTAG clock frequency is too h...

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Problems solved by technology

[0003] Computer processor JTAG circuit logic design errors, emulator signal distortion, JTAG clock frequency is too high, and target processor board-level circuit design errors will cause JTAG to fail to communicate normally. Software and hardware engineers often need to spend a lot of time analyzing and finding that JTAG cannot communicate normally. The reasons affect the debugging efficiency of software and hardware

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