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In-memory computing accelerator and optimization method thereof

An optimization method and accelerator technology, applied in neural architecture, physical implementation, biological neural network models, etc., can solve problems such as insignificant effects, and achieve the effect of reducing power consumption and conversion time

Pending Publication Date: 2021-03-19
SHENZHEN INST OF ADVANCED TECH CHINESE ACAD OF SCI
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  • Abstract
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  • Application Information

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Problems solved by technology

The existing technology generally reduces the power consumption of the ADC by optimizing the internal circuit of the ADC alone, but the effect of this method is not significant

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  • In-memory computing accelerator and optimization method thereof
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  • In-memory computing accelerator and optimization method thereof

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[0024] The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0025] In existing in-memory computing accelerators, the power consumption of ADCs used for analog signal and digital signal conversion can account for more than 50%. It can be seen that the optimal design of ADC is a major bottleneck of current in-memory computing accelerators. However, currently The research on how is basically optimized for the internal circuit implementation of the ADC alone, while ignoring the optimization of the ADC in the in-memory computing accelerator based ...

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Abstract

The invention discloses an in-memory computing accelerator and an optimization method thereof, and relates to the technical field of in-memory computing accelerators. The in-memory computing accelerator comprises a plurality of processing units, and each processing unit comprises a plurality of storage units distributed in an array mode, wherein an ADC is correspondingly arranged at an output portof each column of storage units, and the ADCs are ADCs with configurable resolution ratios; a plurality of resolution control modules, wherein each of the resolution control modules is used for controlling the resolution of the corresponding ADC. The invention also discloses an optimization method of the in-memory computing accelerator. The optimization method comprises the following steps: training and quantifying a neural network model; determining the sparse degree of the whole neural network in the deployment process of the neural network model; calculating the optimal resolution of the ADC in each processing unit according to the sparse degree of each layer of neural network; and dynamically adjusting the resolution of the ADC in each processing unit to the optimal resolution. The method is used for improving the performance of the in-memory computing accelerator.

Description

technical field [0001] The present application relates to the technical field of in-memory computing accelerators, in particular to an in-memory computing accelerator and an optimization method thereof. Background technique [0002] In recent years, neural networks have achieved remarkable success in various practical applications, such as image classification and object detection, but these achievements largely rely on complex neural network models with a large number of parameters and calculations. Deploying these complex neural network models that require a large amount of calculation and data movement to a neural network accelerator (for example, CPU, GPU, FPGA) based on the von Neumann architecture, there will be a "storage wall" problem, that is, data movement The speed cannot keep up with the data processing speed and the energy consumption of data movement is much higher than the energy consumption of data processing. [0003] In-memory computing is a new type of co...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063G06N3/04
CPCG06N3/063G06N3/045
Inventor 陈瑞杨永魁王峥郭伟钰辛锦瀚喻之斌
Owner SHENZHEN INST OF ADVANCED TECH CHINESE ACAD OF SCI