MRAM-NAND controller and data writing method thereof

Abstract

The invention provides an MRAM-NAND controller and a data writing method thereof. The controller comprises an embedded MRAM, a host interface adopting a DDRD-RAM interface standard, an NAND controller, a microcontroller, a buffer and a state register. Due to the fact that the DDR-DRAM interface is adopted as the host interface of the MRAM-NAND controller, the read-write speed of the controller and the read-write speed of a memory bank applied to the controller can be increased. Through caching, the read / write operation efficiency of the controller chip can be effectively improved and stabilized, meanwhile, the working time sequence is adjusted to cope with the compatibility problem of an existing host chip, and the applicability of related products can be improved.

Description

technical field [0001] This application relates to the field of memory technology, in particular to an MRAM-NAND controller and a data writing method thereof. Background technique [0002] Solid State Drives (SSD), referred to as solid disks, are hard disks made of solid-state electronic storage chip arrays, consisting of a control unit and a storage unit (FLASH chip, DRAM chip). The specifications and definitions of interfaces, functions and usage methods of solid-state hard disks are exactly the same as those of ordinary hard disks, and the shape and size of the products are also completely consistent with ordinary hard disks. It is widely used in military, vehicle, industrial control, video surveillance, network monitoring, network terminals, electric power, medical, aviation, navigation equipment and other fields. [0003] Although the development of NAND flash memory technology has promoted the SSD industry, due to the strict requirements on size, it is difficult for e...

AI Technical Summary

Problems solved by technology

[0005]However, the existing MRAM reads very fast, no less than DRAM, but the writing time is relatively long, more than ten times that of DRAM

As a result, when the host performs MRAM read / write operations, the timing design cannot achieve the same or similar design to DRAM, that is, it is different from the current working timing of DRAM-related function chips, which is different from the host chips on the market. Compatibility issues not only limit the applicability, but also affect the promotion of products

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