Neural network in-memory computing device based on communication lower bound and acceleration method

Abstract

The invention relates to the field of neural network algorithms and computer hardware design, in particular to a neural network in-memory computing device based on a communication lower bound and an acceleration method. The invention discloses a neural network in-memory computing device based on a communication lower bound, which comprises a processor, an external memory and a neural network acceleration device. The invention further discloses an acceleration method using the neural network in-memory computing device based on the communication lower bound. According to the method, off-chip-on-chip communication lower bound analysis is taken as a theoretical support, output feature map multiplexing, convolution window multiplexing, balance weight multiplexing and input feature map multiplexing are utilized, and a neural network acceleration device under an in-memory computing architecture and a corresponding data flow scheme are provided, so that off-chip-on-chip data access amount is reduced.

Description

technical field [0001] The invention relates to the fields of neural network algorithms and computer hardware design, and specifically proposes a neural network memory computing device and acceleration method based on a communication lower bound. Background technique [0002] With the rapid development of neural network technology, a large number of neural network algorithms have emerged that have performed very well in applications such as image processing, medical diagnosis, and automatic driving, showing huge advantages. At the same time, in order to obtain better performance, the number and scale of the neural network gradually increase, and the number of weight parameters also gradually increases, resulting in a significant increase in the amount of data movement in the calculation of the neural network algorithm. In order to enable neural network algorithms to be applied in actual scenarios, due to bandwidth constraints, delay requirements, power consumption constraint...

AI Technical Summary

Problems solved by technology

Many studies have proposed neural network acceleration devices and corresponding data flow schemes under the in-memory computing architecture, such as fixed weights, fixed input feature maps, fixed rows-fixed input feature maps, etc. However, these works are based on intuitive observations. However, the optimality of the data flow scheme cannot be guaranteed, and there is a lack of theoretical analysis support

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