Neural network in-memory computing device and acceleration method based on communication lower bound

Abstract

The invention relates to the fields of neural network algorithms and computer hardware design, and specifically proposes a neural network memory computing device and acceleration method based on a communication lower bound. The invention discloses a neural network in-memory computing device based on a communication lower bound, which includes a processor, an external memory and a neural network acceleration device. The invention also simultaneously discloses an acceleration method performed by using the neural network in-memory computing device based on the communication lower bound. The present invention takes off-chip-on-chip communication lower bound analysis as theoretical support, uses output feature map multiplexing and convolution window multiplexing, balances weight reuse and input feature map multiplexing, and proposes a neural network acceleration device under an in-memory computing architecture and Corresponding data flow scheme, thereby reducing off-chip-on-chip data access.

Description

technical field [0001] The invention relates to the field of neural network algorithm and computer hardware design, and in particular provides a neural network in-memory computing device and acceleration method based on a communication lower bound. Background technique [0002] With the rapid development of neural network technology, a large number of neural network algorithms have emerged in image processing, medical diagnosis, automatic driving and other applications, showing great advantages. At the same time, in order to obtain better performance, the number of layers and scale of the neural network gradually increases, and the number of weight parameters also gradually increases, resulting in a large increase in the amount of data movement in the calculation of the neural network algorithm. In order to enable neural network algorithms to be applied in practical scenarios, due to bandwidth limitations, delay requirements, power consumption limitations, privacy protection...

AI Technical Summary

Problems solved by technology

Many studies have proposed neural network acceleration devices and corresponding data flow schemes under the in-memory computing architecture, such as fixed weights, fixed input feature maps, fixed rows-fixed input feature maps, etc. However, these works are based on intuitive observations. However, the optimality of the data flow scheme cannot be guaranteed, and there is a lack of theoretical analysis support

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