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A chip system with remapping function and chip remapping configuration system

A chip system and remapping technology, applied in the direction of logic circuit connection/interface layout, logic circuit coupling/interface using field effect transistors, etc., can solve the problem of high mapping cost and achieve the effect of reducing costs

Active Publication Date: 2022-03-29
HANGZHOU VANGO TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the function of the chip is relatively complex and the number of pins is relatively large, it is too expensive to use a multiplexer to implement chip input and output (I / O) mapping

Method used

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  • A chip system with remapping function and chip remapping configuration system
  • A chip system with remapping function and chip remapping configuration system
  • A chip system with remapping function and chip remapping configuration system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0038] figure 2 It is a schematic structural diagram of the first system-on-a-chip with a remapping function provided by the embodiment of the present application.

[0039] Such as figure 2 As shown, the chip system with remapping function provided by the embodiment of the present application includes: a chip core 101, a chip pin driving circuit 102, and a first chip pin arranged between the chip core 101 and the chip pin driving circuit 102 mapping circuit;

[0040] Wherein, the first chip pin mapping circuit includes an input dynamic interconnection network and an output dynamic interconnection network; the input port of the output dynamic interconnection network is correspondingly connected with the first output port of the chip core 101, and the output port of the output dynamic interconnection network Correspondingly connected with the first output pin of chip pin drive circuit 102; The first input port of the core 101 is correspondingly connected;

[0041] Both the...

Embodiment 2

[0046] image 3 A schematic structural diagram of an output dynamic interconnection network provided by the embodiment of the present application; Figure 4 It is a schematic structural diagram of a B[2] structure provided in the embodiment of this application.

[0047] On the basis of the above examples, if image 3 As shown, in the chip system with remapping function provided by the embodiment of the present application, both the input dynamic interconnection network and the output dynamic interconnection network are specifically: a first Benes network with N input ports and N output ports;

[0048] Both the input port and the output port in the first Benes network are connected to a transmission line with a bit width of 1; N is a power of 2.

[0049] In specific implementation, image 3 Only the output dynamic interconnection network provided by the embodiment of the present application is shown, the structure of the input dynamic interconnection network and the output d...

Embodiment 3

[0057] Figure 5 It is a schematic structural diagram of another output dynamic interconnection network provided by the embodiment of the present application.

[0058] On the basis of the above embodiments, in the chip system with remapping function provided by the embodiment of the present application, both the input dynamic interconnection network and the output dynamic interconnection network specifically include: a second Benes network and a third Benes network;

[0059] Wherein, the N second Benes networks are correspondingly connected to a third Benes network, the second Benes network has K input ports and K output ports, the third Benes network has N input ports and N output ports; the third Benes network Both the input port and the output port of are connected to the bus whose bit width is K; K and N are both powers of 2.

[0060] Considering that pins with the same function or similar functions in the chip are often arranged together, it is often not necessary to est...

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Abstract

This application discloses a chip system with a remapping function and a chip remapping configuration system. The input dynamic interconnection network and the output dynamic interconnection network are respectively set for the input signal and output signal between the chip core and the chip pin drive circuit. ; Wherein, the input port of the output dynamic interconnection network is correspondingly connected with the first output port of the chip core, and the output port of the output dynamic interconnection network is correspondingly connected with the first output pin of the chip pin drive circuit; the input dynamic interconnection network The input port of the input port is correspondingly connected with the first input pin of the chip pin driving circuit, and the output port of the input dynamic interconnection network is correspondingly connected with the first input port of the chip core. The non-blocking network structure adopts a recursive way to expand the structure, thus delaying the increase of the number of intersection points with the number of incoming and outgoing lines compared with the existing technology of using a multiplexer to realize chip pin remapping, thereby reducing The cost of implementing chip pin remapping.

Description

technical field [0001] The present application relates to the field of chip technology, in particular to a chip system with a remapping function and a chip remapping configuration system. Background technique [0002] In the process of designing the chip, the R&D team often repeatedly considers how to arrange the chip pins, and needs to comprehensively consider various application scenarios to obtain a more reasonable arrangement. However, as the chip design technology becomes more and more mature, the functions of the chip become more and more complex, and there are more and more pins. Often, different pin arrangements are required in different application scenarios. [0003] Therefore, after the chip is manufactured, if the arrangement of the chip pins can be remapped by the software configuration, then the user can define the pins according to their own application requirements, which greatly improves the flexibility of the chip and saves the chip design process. Time fo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/0185
CPCH03K19/0185
Inventor 肖晓辉何杰谭年熊
Owner HANGZHOU VANGO TECH
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