Method and device for starting reconfiguration in SEC verification and FPGA

Abstract

The invention discloses a method and device for starting reconfiguration in SEC verification and an FPGA. The method comprises the steps that in the process that an FPGA executes active configuration, a register is used for recording the initial address of a first configuration data file selected by the configuration and marking information about whether the first configuration data file is reconfigured by a user or not; the method also includes: when the FPGA enters a user mode, responding to the fact that the SEC verification result is not passed, and when the FPGA is reconfigured, determining an initial address of a second configuration data file based on the mark information recorded in the register, wherein when the mark information shows that the last configuration is user reconfiguration, the initial address of the second configuration data file is the initial address of the first configuration data file recorded in the register; and obtaining the second configuration data file from the initial address of the second configuration data file to reconfigure the FPGA. According to the invention, the problem that the reconfigured FPGA function is sometimes different from the FPGA function before reconfiguration after the SEC verification fails is solved.

Description

technical field [0001] The invention belongs to the technical field of FPGA (Field-Programmable Gate Array, Field Programmable Gate Array), in particular to a method, device and FPGA for starting reconfiguration in SEC (Soft Error Correcting) verification. Background technique [0002] The FPGA configuration memory is distributed throughout the entire FPGA chip and is the largest storage unit in the FPGA chip. Among them, the data stored in the FPGA configuration memory controls configurable logic resources such as FPGA routing resources and look-up tables, and determines the behavior of the user circuit. Once the configured data is wrong, the FPGA will not be able to realize the designed function. [0003] There are multiple configuration modes for FPGA configuration, such as active configuration mode, JTAG configuration mode, and passive serial configuration mode. Among them, for the active configuration mode, after the FPGA is powered on, it will automatically send the c...

AI Technical Summary

Problems solved by technology

Among them, the data stored in the FPGA configuration memory controls configurable logic resources such as FPGA wiring resources and look-up tables, and determines the behavior of the user circuit. Once the configured data is wrong, the FPGA will not be able to realize the designed function.

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