Compensation circuit applied to logic chip and time sequence compensation method
A compensation circuit and logic chip technology, applied to logic circuits with logic functions, etc., can solve problems such as cumbersome calculations, narrow sampling timing windows of logic chips, and unsatisfactory sampling timing of voltage fluctuations, and achieve the effect of reducing complexity
Active Publication Date: 2021-07-23
HUNAN GOKE MICROELECTRONICS
View PDF11 Cites 0 Cited by
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
[0002] With the rapid development of power electronics technology, various types of logic chips are applied. Among them, the data acquisition rate of many logic chips is getting higher and higher, which will lead to narrower and narrower sampling timing windows of logic chips.
[0003] During the data sampling process of the logic chip, the voltage fluctuation or temperature fluctuation of the logic chip may cause the sampling timing that already meets the data sampling requirements to become unsatisfactory.
In the prior art, in order to compensate the sampling timing of the logic chip, it is not only necessary to design a complex compensation circuit, but also to perform cumbersome calculations to compensate the sampling timing of the logic chip
At present, there is no effective solution to this technical problem
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View moreImage
Smart Image Click on the blue labels to locate them in the text.
Smart ImageViewing Examples
Examples
Experimental program
Comparison scheme
Effect test
Embodiment approach
[0052] Based on the above embodiments, this embodiment further explains and optimizes the technical solution, please refer to figure 2 , figure 2 A structural diagram of another compensation circuit applied to a logic chip provided by an embodiment of the present invention. As a preferred implementation manner, the oscillating ring includes: a second multiplexer and a delay unit composed of a plurality of mutually series-connected NOT gates;
[0053] Wherein, the output end of the delay unit is connected with the input end of the counter, each input end of the second multiplexer is connected with the output end of each NOT gate respectively, and the output end of the second multiplexer is connected with the input end of the delay unit .
[0054] In the actual operation process, you can also use the second multiplexer and a simple logic gate circuit to build an oscillation ring. For details, please refer to figure 2 , in the oscillation ring, the oscillation frequency of ...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More PUM
Login to View More Abstract
The invention discloses a compensation circuit applied to a logic chip. The compensation circuit comprises a counter, a clock trigger, a first multiplexer and an oscillation ring which are connected with the logic chip, wherein the output end of the clock trigger is connected with the input end of the first multiplexer, the control end of the first multiplexer is connected with the output end of the counter, the output end of the first multiplexer is connected with the control end of the counter, and the output end of the oscillation ring is connected with the input end of the counter. Obviously, since the compensation circuit can achieve the purpose of compensating the sampling time sequence of the logic chip only according to the count value of the counter, the complexity of compensating the sampling time sequence of the logic chip can be obviously reduced through the setting mode.
Description
technical field [0001] The invention relates to the technical field of power electronics, in particular to a compensation circuit applied to a logic chip and a timing compensation method. Background technique [0002] With the rapid development of power electronics technology, various types of logic chips are applied. Among them, the data acquisition rate of many logic chips is getting higher and higher, which will lead to narrower and narrower sampling timing windows of logic chips. [0003] During the data sampling process of the logic chip, voltage fluctuations or temperature fluctuations of the logic chip may cause the sampling timing that originally meets the data sampling requirements to become unsatisfactory. In the prior art, in order to compensate the sampling timing of the logic chip, it is not only necessary to design a complex compensation circuit, but also to perform cumbersome calculations to compensate the sampling timing of the logic chip. Currently, there i...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More Application Information
Patent Timeline
Login to View More Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/20
CPCH03K19/20Y02D10/00
Inventor 黄锐汪再金刘洋
Owner HUNAN GOKE MICROELECTRONICS