Semiconductor structure and forming method thereof

Abstract

A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a low-k dielectric layer over the second dielectric layer, a second dielectric layer on the high resistance layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer. The method also relates to a forming method of the semiconductor structure.

Description

technical field [0001] Embodiments of the invention relate to semiconductor structures and methods of forming the same. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (eg, the number of interconnected devices per chip area) typically increases while geometry size (eg, the smallest component (or line) that can be created using a fabrication process) decreases. This scaling down process typically provides benefits through increased production efficiency and reduced associated costs. [0003] As devices are scaled down, manufacturers have begun to use new and different materials and / or combinations of materials to facilitate device scaling. Scaling down alone and in combination with new and di...

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Problems solved by technology

Scaling down alone and in combination with new and different materials also raises challenges of larger geometries that previous generations may not have encountered

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