A multi-bit storage device
A technology of reading and writing bits and multiplying and accumulating, which is applied in the field of in-memory computing, can solve the problems of small data bit width and large area, and achieve the effect of increasing data bit width, reducing area, and improving efficiency
Active Publication Date: 2021-11-26
中科南京智能技术研究院
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Problems solved by technology
The traditional 8T SRAM structure has a large number of transistors, a large area, and requires a small input data bit width, which does not meet the current needs
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[0040] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0041] The purpose of the present invention is to provide a multi-bit storage and calculation device, which can reduce the number of transistors, realize the reduction of the area, and improve the calculation efficiency.
[0042] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodi...
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The invention relates to a multi-bit storage and calculation device. In the device, the storage unit array module is connected with the input driver, read-write bit line driver module, row decoder and voltage equalization module; the voltage equalization module is connected with the multiplication and accumulation readout control module; the input driver is used to input data and control the input The data on the line, so that the data on the input bit line and the weight stored in the storage array are calculated; the row decoder is used to control the storage of the weight and the selection of the weight through the output word line WL; the read and write bit line drive module is used for The storage and readout of weights are realized through the output bit lines BL and BLB; the storage and calculation unit array module is used to store and calculate according to the weights, and obtain the output results; the voltage equalization module is used to charge-share the output results; multiply and accumulate The readout control module is used to output the calculation result after charge sharing. The invention can reduce the number of transistors, realize the reduction of the area, and improve the calculation efficiency.
Description
technical field [0001] The invention relates to the field of in-memory calculation, in particular to a multi-bit storage and calculation device. Background technique [0002] Deep Convolutional Neural Networks (DCNNs) are developing rapidly in fields such as artificial intelligence. With its gradual development, more and more issues such as size, efficiency, and energy consumption need to be considered. In the traditional calculation process, the weight is moved between the memory and the operation unit, which does not meet the requirements of low power consumption. In-memory computing (IMC) is increasingly attractive for DCNN acceleration. The traditional 8T SRAM structure has a large number of transistors and a large area, and requires a small input data bit width, which does not meet the current needs. [0003] Therefore, there is an urgent need for an in-memory computing device that changes the traditional computing operations, reduces the number of transistors, reduce...
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IPC IPC(8): G06F7/523G06N3/04G06N3/063
CPCG06F7/523G06N3/063G06N3/045
Inventor 乔树山陶皓尚德龙周玉梅
Owner 中科南京智能技术研究院