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A system-level fan-out packaging structure using a glass substrate and a processing method thereof

A technology of glass substrate and packaging structure, which is applied in the direction of semiconductor/solid-state device components, semiconductor devices, electrical components, etc., to improve production efficiency and simplify the production process.

Active Publication Date: 2022-05-17
GUANGDONG UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It can solve the problem that the number of pins restricts chip packaging. The design of conductive metal packaging greatly improves the production efficiency of circuit boards, and can realize integrated packaging of multi-layer chips with different sizes, different heights and different performances, which has a good application prospect.

Method used

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  • A system-level fan-out packaging structure using a glass substrate and a processing method thereof

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Experimental program
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Effect test

Embodiment

[0030] Please refer to the attached figure 1 Prepare a glass substrate 1 of 9*9*1mm, deposit a layer of Ti-Cu layer 2 on the upper surface of the glass substrate 1 by physical vapor deposition method, and coat a layer of photoresist. The photoresist is made of photosensitive polyamide It is made of imine, exposed and developed to reveal the required pattern, a layer of copper plating 3 is electroplated on the Ti-Cu metal layer, and the photoresist and redundant Ti-Cu layer 2 are removed to complete the production of the first rewiring layer.

[0031] Make chip bumps for each chip 4 by electroplating, move the prepared chip 4 to the corresponding position above the rewiring layer, and use reflow soldering to connect the chip 4 to the rewiring layer, and complete in order from large to small.

[0032] Wire bonding is used to stack copper balls at the position where the first rewiring layer is to be electrically connected to the second rewiring layer, and the copper balls are con...

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Abstract

The invention discloses a system-level fan-out packaging structure using a glass substrate and a processing method thereof, belonging to the technical field of chip packaging. Including glass substrate, rewiring layer, chip and conductive metal and several epoxy molding layers, the glass substrate is placed on the bottom layer, and the rewiring layer is placed between the glass substrate and the epoxy molding layer and between each layer of epoxy molding layer, the chip It is welded on the rewiring layer, a number of conductive metals are stacked on the rewiring layer, and epoxy molding compound is filled between the chip and the conductive metal in the epoxy molding layer. The invention can solve the problem that the number of pins restricts chip packaging, and the design of conductive metal packaging greatly improves the production efficiency of circuit boards, and can realize integrated packaging of multi-layer chips with different sizes, different heights and different performances, and has good application prospects.

Description

technical field [0001] The invention belongs to the technical field of chip packaging, in particular to a system-level fan-out packaging structure using a glass substrate and a processing method thereof. Background technique [0002] Since Moore's Law was put forward, integrated circuits have followed Moore's Law and developed rapidly, that is, when the price remains unchanged, the number of components that can be accommodated on an integrated circuit will double every 18-24 months, and the performance will also increase. Double it. However, as the size of the integrated circuit can be reduced to the nanometer level and gradually approaching its physical limit, the method of reducing the feature size can no longer further improve the performance and function of the integrated circuit. However, the demand of the microelectronics market continues to grow, so the development of integrated circuits is facing a series of problems and challenges. [0003] The emerging fan-out pa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/15H01L23/31H01L25/065
CPCH01L23/15H01L23/3121H01L25/0652H01L2225/06524
Inventor 杨冠南刘宇黄钰森崔成强张昱
Owner GUANGDONG UNIV OF TECH