Multi-device graded embedding packaging substrate and manufacturing method thereof

Abstract

The invention discloses a multi-device graded embedding packaging substrate. The packaging substrate comprises a first dielectric layer, a second dielectric layer and a third dielectric layer, the first dielectric layer comprises a first conduction copper column layer and a first device placing opening frame, and the second dielectric layer comprises a first wiring layer located in the lower surface of the second dielectric layer. A second conduction copper column layer and a heat dissipation copper block layer are arranged on the first wiring layer, the third dielectric layer comprises a second wiring layer, a third conduction copper column layer is arranged on the second wiring layer, the first wiring layer and the second wiring layer are in conduction connection through the first conduction copper column layer, a first device is mounted at the bottom of the first device placing opening frame, and a terminal of the first device is conductively connected with the second wiring layer. A second device placing opening frame penetrating through the first dielectric layer, the second dielectric layer and the third dielectric layer is further included, a second device is mounted at the bottom of the second device placing opening frame, and the thickness difference exists between the second device and the first device. The invention further discloses a manufacturing method of the multi-device graded embedding packaging substrate.

Description

technical field [0001] The invention relates to an electronic device packaging structure, in particular to a multi-device embedded packaging substrate and a manufacturing method thereof. Background technique [0002] With the increasing development of electronic technology, the demand for electronic products tends to be highly functional and miniaturized. As the miniaturization of chips is approaching the limit, how to reasonably package multiple chips and other components to achieve high functionality and miniaturization has become an important research topic in the current industry. At the same time, due to cost and efficiency considerations, panel-level packaging has also become a current trend. In the process of making the substrate, components such as chips are embedded in the substrate, which can effectively reduce the packaging volume and improve output efficiency. , At the same time, compared with wafer-level packaging, the cost is greatly reduced. After continuous...

AI Technical Summary

Problems solved by technology

[0004] For traditional board-level embedded packaging substrates, the most common method for embedding multiple chips and other components is to spread all the components horizontally for one-time embedding. It is difficult to integrate chips and other components through a free design. Embedded packaging at the most reasonable substrate layer; traditional board-level embedded packaging methods mostly embed multiple chips and other components on the same layer at one time, which requires that the thickness difference between chips and other components cannot Too large, otherwise it will affect the quality of embedded packaging; especially for components with I / O on both sides that need to be fan-out, if the thickness difference is too large, it is difficult to achieve I / O fan-out of components with smaller thickness

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