Serial-to-parallel conversion circuit

Abstract

The invention provides a serial-to-parallel conversion circuit, and the circuit comprises a data shift unit which is used for receiving serial data, a positive polarity associated clock and a negative polarity associated clock, sampling the serial data through the positive polarity associated clock and the negative polarity associated clock to obtain double-edge sampling data, then synchronizing the double-edge sampling data to a clock domain of the negative polarity associated clock for data shift, and obtaining and outputting shift data; a clock generation unit which is used for receiving the negative polarity associated clock and generating a parallel reading clock for reading parallel data according to the negative polarity associated clock; and a parallel selection output unit which is used for selecting the shift data as parallel data output according to the parallel reading clock. According to the invention, the current data can be output at the current time without depending on the reading clock of subsequent data, the time delay of data reading is reduced, and the reading efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of serial-to-parallel conversion, in particular to a serial-to-parallel conversion circuit. Background technique [0002] The application of field programmable gate array (FPGA Field Programmable GateArray, FPGA) for accessing dynamic random access memory (Dynamic Random Access Memory, DRAM) is very common. [0003] However, since the DRAM interface is a transmission mode of source synchronous burst mode, during the reading process, data may be written or other operations may be performed intermittently during reading, so these intermittent operations will reduce the efficiency of the DRAM interface. The traditional DRAM reading serial-to-parallel conversion circuit needs to use the next data reading clock to obtain the data read this time, such as figure 1 As shown, if the next reading time is longer or other operations are mixed in the middle, the reading time interval will be very long, which increases t...

AI Technical Summary

Problems solved by technology

The traditional DRAM reading serial-to-parallel conversion circuit needs to use the next data reading clock to obtain the data read this time, such as figure 1 As shown, if the next reading time is longer or other operations are mixed in the middle, the reading time interval will be very long, which increases the reading delay.

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