Turbo decoder fault tolerance method based on DWC

A decoder and decoding technology, which is applied in the fault tolerance field of DWC-based turbo decoders, can solve the problem that the overall protection of the decoder cannot be realized, and achieve the effect of reducing resource overhead and excessive protection.

Inactive Publication Date: 2021-10-26
TIANJIN UNIV
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AI Technical Summary

Problems solved by technology

Although these methods take into account the fault tolerance of the Turbo decoder, they are only effective for soft errors in user storage, and cannot achieve overall protection for the decoder.

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  • Turbo decoder fault tolerance method based on DWC
  • Turbo decoder fault tolerance method based on DWC
  • Turbo decoder fault tolerance method based on DWC

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Embodiment Construction

[0028] The Turbo decoder that adopts the Log-MAP decoding algorithm is used for the implementation example of the present invention, and the structure of the decoder is as follows figure 1 shown. The generation matrix of the Turbo code is G=[1 1 0 1; 1 0 1 1], the code rate is 1 / 3, and the information sequence length is 256. In order to ensure that the final state of the encoder returns to zero during the encoder, each component encoder generates 3 additional information bits and 3 check bits, so the length of the encoded sequence is 256*3+(3+3)*2= 780, which is the input sequence length of the decoder. The Turbo decoder iterates 8 times in total, and if one component decoding is counted as one time, it is 16 times.

[0029] 1) The proposal of the DWC fault-tolerant scheme in the present invention is based on the analysis of the influence of the SEU on the internal variables of the Turbo decoder. Through the fault injection experiment of FPGA, it is found that the absolute ...

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Abstract

The invention relates to a Turbo decoder fault-tolerant method based on DWC. The method comprises the following steps that: two Turbo decoders decode the same decoding input at the same time, and each Turbo decoder outputs three pieces of information after the decoding is finished; the decoding output sequences C of the two Turbo decoders are compared, and if the two decoding output sequences are completely the same, it is considered that no fault occurs in the two Turbo decoders; if the output sequences of the two Turbo decoders are not completely the same, it is judged that one decoder breaks down, then the sum M of LLR absolute values of last iteration of one Turbo decoder is compared with the sum M of LLR absolute values of last iteration of the other Turbo decoder at the moment, it is judged that a larger value in the sum of the two LLR absolute values comes from the fault-free Turbo decoder, and a corresponding decoding result serves as final decoding output; and if the sum M of the LLR absolute values of one Turbo decoder is identical with the sum M of the LLR absolute values of the other Turbo decoder, whether the result of last iterative decoding is the same as the result of previous iteration or not is continuously compared.

Description

technical field [0001] The invention relates to a DWC-based Turbo decoder error-tolerant method. Background technique [0002] Communication is an important element of space systems. In order to weaken the adverse effects of noise, channel coding technology is usually used to improve the reliability of information transmission, but decoding has also become one of the most complex modules in the space platform. Due to its strong error correction capability and acceptable decoder complexity, Turbo codes have been widely used in terrestrial communication systems, such as 3G and 4G, and satellite communication systems, such as SkyTura and BMSAT. On the other hand, On-Board Processing (OBP) has been widely used in space communication processing platforms in recent years due to its flexibility and good performance. The SRAM FPGA has rich logic resources, good reconfigurability, and can support online upgrades, so it is an ideal choice for the OBP platform. However, SRAM-FPGA is...

Claims

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Application Information

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IPC IPC(8): H03M13/29
CPCH03M13/2957
Inventor 高镇魏晓慧张玲玲裴静刘玥
Owner TIANJIN UNIV
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