A Selective Protection Method Based on Viterbi Decoder

A decoder, a selective technology, applied in the direction of encoding, code conversion, encoding components, etc., can solve the problem that the overall behavior of the Viterbi decoder is not fully utilized, and the processing capacity and functional diversity of the space platform are limited. problem, to achieve the effect of reducing resource overhead and reducing over-protection

Active Publication Date: 2021-06-08
TIANJIN UNIV
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  • Abstract
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  • Claims
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Problems solved by technology

On the other hand, under the same system resource limitation, if the TMR scheme is used, the overall processing capacity of the system will be reduced to one-third of the unprotected case, which will greatly limit the processing capacity and functional diversity of the space platform sex
In addition, in the traditional three-mode protection scheme, the overall behavior characteristics of the Viterbi decoder and its own fault tolerance are not fully utilized

Method used

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  • A Selective Protection Method Based on Viterbi Decoder
  • A Selective Protection Method Based on Viterbi Decoder
  • A Selective Protection Method Based on Viterbi Decoder

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example 1

[0028] 1) Convolutional coding (3, 1, 6) is used in the implementation example of the present invention. The bit length of the information to be encoded in the encoder is 54, and 6 zeros are added at the end of the sequence to realize the return-to-zero code, so the encoded information length is L=3*(54+6)=180. According to the formulas (1) to (4) in the above specific implementation manner, the bit widths of the PM and BM registers are calculated as 13 (12+1) and 8 (7+1) respectively, and an extra bit is added to indicate that the highest bit is used to represent the sign bit. Since k=1, m=3, each step of decoding in the decoding process has 2 6 = 64 states, each state has 2 1 = 2 transition paths are used to find the optimal path for each state in each step in the decoding process.

[0029] 2) The Viterbi decoder is implemented based on FPGA. The whole decoder is mainly composed of four modules: TopController: contains 23 bits of enabling signals to control other modules o...

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Abstract

The invention relates to a selective protection method based on a Viterbi decoder. On the basis of realizing the Viterbi decoder based on FPGA and calculating the bit width of the register, it includes: selectively protecting the Viterbi decoder: SEU tolerance Register bits with a value of 0 adopt triple-mode protection: add two bits of redundant information to all bit positions at the same time, store the same information as the original bit position, and the final result is based on any two bits of the same bit information. Two-mode protection is performed on the bit position of the SEU fault-tolerant register: each bit adds a corresponding bit of redundant information, stores the same information as the original bit position, and then adds a logical AND gate, and the output result of the AND gate is The protected bit position final result.

Description

technical field [0001] The invention relates to a selective protection method based on a Viterbi decoder. Background technique [0002] Communications are a key element of space systems, especially satellites. In fact, in many cases, the main purpose of satellites is to provide communications for terrestrial services. Therefore, these satellites need to be able to have onboard processing of the received signals. This requires complex circuitry in many cases. For example, in order to achieve an acceptable bit error rate (BER) even at low signal-to-noise ratio (SNR), the signal at the transmitting end usually has some form of encoding, and errors are then corrected at the receiver. When convolutional coding is used at the transmitter, the receiver typically implements a Viterbi decoder to detect and correct errors. The decoder can be implemented in software running on the processor. However, in the space environment, there are radiation particles. When the space radiation...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/23H04L1/00
CPCH03M13/235H04L1/0054
Inventor 高镇闫丽娜朱锦华
Owner TIANJIN UNIV
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