Cascading method of PCIe signal processing card

A signal processing and processing card technology, applied in the cascade field of PCIe signal processing cards, can solve the problems of limited FPGA resources, limitation of the acceleration capability of a single PCIe card, etc., and achieve the effect of breaking through the bottleneck of limited acceleration capability.

Pending Publication Date: 2021-11-09
成都博宇利华科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a cascading method of PCIe signal processing cards, which is used to solve the problem of being limited by FPGA resources when using FPGA to realize PCIe signal processing hardware acceleration in the prior art, and to further solve the problem of PCIe connection bandwidth limitation. The acceleration capability of a single PCIe card is limited

Method used

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  • Cascading method of PCIe signal processing card
  • Cascading method of PCIe signal processing card
  • Cascading method of PCIe signal processing card

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0038] combined with figure 1 and image 3 As shown, a method for cascading PCIe signal processing cards, including:

[0039] Step S110, cascading multiple identical PCIe signal processing cards through inter-board data high-speed cascading channels, one of the PCIe signal processing cards is connected to the FMC sub-card as the main card, and the remaining PCIe signal processing cards are used as co-processing cards. A PCIe signal processing card communicates with the host computer through the PCIe slot;

[0040] Step S120, the FMC sub-card sends the collected raw data to the main card, and the main card slices and encapsulates the original data to obtain packaged data, and the package header of the packaged data contains information such as the card ID and serial number of the corresponding PCIe signal processing card , the data format of the encapsulation header is shown in the following table:

[0041]

[0042] Step S130, the main card transmits all the data to the c...

Embodiment 2

[0045] A method for cascading PCIe signal processing cards, comprising:

[0046] In step S210, multiple identical PCIe signal processing cards are cascaded through inter-board data high-speed cascading channels, one of the PCIe signal processing cards is connected to the FMC sub-card as the main card, and the remaining PCIe signal processing cards are used as co-processing cards. A PCIe signal processing card communicates with the host computer through the PCIe slot;

[0047] Step S220, the FMC sub-card sends the collected raw data to the main card, and the main card slices and encapsulates the original data to obtain packaged data, and the package header of the packaged data contains the board ID and data block serial number of the corresponding PCIe signal processing card and other information;

[0048] Step S230: The main card takes out the data corresponding to its own card ID from the packaged data, and then sends the remaining data to the next-level co-processing card t...

Embodiment 3

[0053] combined with figure 2 As shown, a method for cascading PCIe signal processing cards, including:

[0054] In step S310, multiple identical PCIe signal processing cards are cascaded through the inter-board data high-speed cascading channel, one of the PCIe signal processing cards is connected to the FMC sub-card as the main card, and the remaining PCIe signal processing cards are used as co-processing cards. A PCIe signal processing card communicates with the host computer through the PCIe slot;

[0055] Step S320: the host computer slices and encapsulates the modulated data to obtain the encapsulated data, and the encapsulation header of the encapsulated data contains information such as the card ID and the data block serial number of the corresponding PCIe signal processing card;

[0056] Step S330: The host computer sends all packaged data to each PCIe signal processing card through the PCIe slot, and the FPGA on each PCIe signal processing card processes the data a...

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Abstract

The invention discloses a cascading method of PCIe signal processing cards, a plurality of same PCIe signal processing cards are cascaded through an inter-board data high-speed cascading channel, one PCIe signal processing card is connected with an FMC daughter card to serve as a main card, the rest PCIe signal processing cards serve as co-processing cards, and each PCIe signal processing card is in communication connection with an upper computer through a PCIe slot; the FMC daughter card sends collected original data to the main card for fragmentation and packaging, and a packaging head comprises a board card ID corresponding to the PCIe signal processing card; the main card transmits all data to the co-processing cards through an inter-board data high-speed cascade channel, each co-processing card processes the data matched with the ID of the own board card and transmits the processing result data to the upper computer, and the upper computer recombines the data. According to the invention, the problem that hardware acceleration is limited by FPGA resources is solved, and an elastically expanded cascade channel is realized; the method is suitable for collecting and transmitting scenes.

Description

technical field [0001] The invention relates to the technical field of signal processing, in particular to a method for cascading PCIe signal processing cards. Background technique [0002] A PCIe-based signal processing card usually uses FPGA to realize hardware acceleration of signal processing. The application scenario is mainly to insert it into the PCIe slot of a PC or server, and after the hardware operation and processing of the external mid-radio frequency signal, the data result is transmitted to the upper computer CPU for further processing. For example, in a specific FPGA device, the hardware DDC or FFT operation of multiple channels is realized. However, due to the following two limitations, the acceleration capability of a single PCIe card reaches the ceiling: (1) Limited by FPGA resources. When the logic resources in the FPGA are used up, hardware acceleration of more channels cannot be realized, and a larger-scale FPGA device can only be replaced. (2) Limit...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/12G06F15/163
CPCG06F13/124G06F15/163G06F2213/0026
Inventor 杨庸
Owner 成都博宇利华科技有限公司
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