Circuit structure of slave chip for realizing full duplex communication of serial interface

Abstract

The invention relates to a circuit structure of a slave chip for realizing full duplex communication of a serial interface, and the slave chip comprises an auxiliary clock generation module, a sampling module and a shifting module, wherein a sampling clock signal sck_sample and a shifting clock signal sck_shift which are not synchronized with a main frequency clock signal CLK respectively control a sampling module to sample a serial data input signal SDI, and the shifting module is triggered to shift data in a parallel data packet needing to be sent. And the shifting module outputs a corresponding serial data output signal SDO. By adopting the circuit structure, the problem that a serial data output signal SDO is delayed relative to a communication clock signal SCK in the prior art can be effectively solved, data transmission can be effectively and accurately carried out, the cost is low, and the application range is wide.

Description

technical field [0001] The invention relates to the field of communication, in particular to the field of serial interface synchronous transmission, and specifically refers to a circuit structure of a slave chip for realizing serial interface full-duplex communication. Background technique [0002] As one of the computer communication methods, serial communication mainly plays the role of data transmission between the host or slave and peripherals. Serial communication has the characteristics of less transmission lines and low cost. [0003] If the serial interface wants to achieve high-speed transmission rate and transmission efficiency, it mostly adopts full-duplex, clock-synchronized communication mode, and supports master and slave modes. Only the serial data line and the synchronous clock line are occupied on the pins of the chip, and are connected to external devices through 4 pins, which are used to transmit the serial data input signal SDI, and are used to transmit ...

AI Technical Summary

Problems solved by technology

[0008] That is, in the full-duplex high-speed serial interface design in the prior art, the communication clock signal SCK and the main frequency clock signal CLK of the communication interface in the slave mode are asynchronous signals, if the communication clock signal SCK and the main frequency clock signal CLK are used in the current There is a method to synchronize and then perform data shift processing, which will cause a delay of the serial data output signal SDO relative to the communication clock signal SCK

In the prior art, the frequency of the main frequency clock signal CLK is increased as much as possible, and the delay of the communication clock signal SCK' relative to the communication clock signal SCK after the communication clock signal SCK is synchronized by the main frequency clock signal CLK is reduced as much as possible to reduce the serial frequency. The delay of the line data output signal SDO relative to the communication clock signal SCK, but this increases the circuit chip area and cost

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