A clock generation method and system based on a standard frequency signal

Abstract

The present invention provides a clock generation method and system based on a standard frequency signal. The scheme includes: firstly, a frequency detector detects the frequency of an input clock, a reference clock, and a standard frequency signal, and then judges the frequency of the input clock, a reference clock, and a standard frequency signal. Whether the frequency relationship among them satisfies the preset condition is obtained to obtain a judgment result, and finally according to the judgment result, the working mode for generating the output clock is adjusted to obtain the output clock. In this application, a standard frequency signal with long-term frequency stability is used as a reference to obtain a stable clock signal, thereby ensuring the accuracy and stability of the clock signal.

Description

technical field [0001] The invention relates to the technical field of electronic circuits, in particular to a method and system for generating a clock based on a standard frequency signal. Background technique [0002] Nowadays, in the high-speed 5G communication network, many links require precise and stable clocks to ensure efficient and high-quality communication on the network, and there are high requirements for the precision, accuracy and stability of the clock. If the precision, accuracy and stability of the clock are poor, it will affect the synchronization work of the communication network, resulting in poor performance of the communication network. [0003] In the prior art, a synchronized output clock is mainly obtained by processing an input clock and a reference clock through a phase-locked loop. When the frequency of the input clock is stable and within the normal range, the output clock is obtained based on the frequency of the input clock; when the frequenc...

AI Technical Summary

Problems solved by technology

In this method, when the reference clock ages and the frequency of the reference clock deviates, it will be mistaken for a deviation in the frequency of the input clock, resulting in the output clock being erroneously output with the deviation of the reference clock.

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