A storage and calculation integrated circuit with multiplexing weight

Abstract

The present invention relates to an integrated storage and calculation circuit for multiplexing weights, which is characterized in that it comprises: an array of SRAM calculation units; each SRAM calculation unit includes a storage unit, a tube T1, a tube T2, a tube T3 and a tube T4, and the calculation sub-module includes a tube TN1, tube TN2, tube TP1, tube TP2, coupling capacitor C1 and coupling capacitor C2, the gate of tube T1 and the gate of tube T3 are all connected to the first weight storage point of the storage unit, the gate of tube T2 and the gate of tube T4 The gates are all connected to the second weight storage point of the storage unit; the coupling capacitor C1 is used to realize the NOR calculation of the input of the inverse input terminal and the weight value corresponding to the first weight storage point, and the coupling capacitor C2 is used to realize the input of the input terminal and the weight value corresponding to the first weight storage point. Exclusive OR calculation of weight values ​​of a weight storage point. The invention improves the utilization rate of the weight of the storage unit and reduces the read-write interference of the weight at the same time.

Description

technical field [0001] The invention relates to the field of in-memory computing, in particular to a storage-computation integrated circuit for multiplexing weights. Background technique [0002] Edge computing plays a vital role in the AI ​​ecosystem and AI-based Internet of Things (AIoT) devices to provide better real-time user experience and privacy. Energy efficiency is a priority driving the development of intelligent edge devices; however, the traditional Von Neumann architecture consumes a lot of energy for data movement between off-chip memory and processing units, which is an urgent bottleneck for edge computing. [0003] Computing in memory (CIM) eliminates the boundary between memory and processing units by implementing computing operations in memory macros, so in-memory computing is a promising approach to improve the energy efficiency of AI edge computing and AIoT devices. [0004] CIM can be implemented with volatile memory (eg SRAM-CIM) or non-volatile memory...

AI Technical Summary

Problems solved by technology

[0005] But when doing calculations, the traditional on-chip static random access memory SRAM needs 6 transistors to store a weight value, which will consume more hardware resources. At the same time, the traditional calculation method of multiplying a single input by a single weight makes the use of weight rate is not high

In the case of high hardware resource consumption and low utilization rate, SRAM-based in-memory computing will not be dominant in terms of power consumption or area

[0006] At the same time, the traditional calculation method is to accumulate the calculation results (generally expressed as voltage) on the read bit line, which will easily lead to two consequences. One: if the voltage swing of the bit line is too large, the weight stored in 6TSRAM will be rewritten, that is The so-called read and write interference, second, the voltage margin of the read and write results on the read bit line is small, which is not conducive to the digital conversion of the analog-to-digital converter

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