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Nanosheet transistor stack

A transistor, p-type technology, applied in transistors, nanotechnology, nanotechnology, etc.

Pending Publication Date: 2022-02-22
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, planar transistors are approaching the process limit for device scaling

Method used

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  • Nanosheet transistor stack
  • Nanosheet transistor stack
  • Nanosheet transistor stack

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0014] The detailed description set forth below in connection with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details to provide a thorough understanding of various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts.

[0015] As used herein, the term "coupled to" in the various tenses of the verb "coupled" may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., element A Indirect connection with element B) to operate some intended function. In the context of electrical components, the term "coupled to...

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Abstract

Methods and apparatuses for different types of non-planar transistors within a stack are presented. The apparatus includes a p-type transistor and an n-type transistor arranged in a stack vertically above a substrate, the p-type transistor and the n-type transistor being non-planar transistors. The p-type transistor includes a p-type channel (210) and a first set of work function layer (213). The first set of work function layer surrounds the p-type channel. The p-type channel is configured for p-type conductivity based on the first set of work function layer. The n-type transistor includes an n-type channel (220) and a second set of work function layer (223). The second set of work function layer surrounds the n-type channel. The n-type channel is configured for n-type conductivity based on the second set of work function layer. The first set of work function layer and the second set of work function layer are different.

Description

[0001] Priority claims under 35 U.S.C. §119 [0002] This patent application claims priority to U.S. Nonprovisional Application No. 16 / 918,770, filed July 1, 2020, entitled "Nanosheet Transistor Stack," which claims priority to U.S. Nonprovisional Application No. 16 / 918,770, filed July 3, 2019, entitled " Nanosheet Transistor Stack," the priority of U.S. Provisional Application Serial No. 62 / 870,453, the entire contents of which are expressly incorporated herein by reference. technical field [0003] The present disclosure generally relates to methods and apparatus having a stack of non-planar transistors, and more particularly to different types of non-planar transistors within the stack. Background technique [0004] Emerging applications such as artificial intelligence and 5G communications require ever-increasing performance and power reduction of computing devices. One way to increase performance and reduce power is to shrink the size of the transistors that serve as ...

Claims

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Application Information

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IPC IPC(8): H01L27/092H01L29/06H01L29/775H01L29/78H01L21/8238H01L21/033H01L21/336
CPCH01L27/0922H01L29/0673H01L29/775H01L29/66795H01L21/823821H01L21/823807H01L21/0337H01L29/785H01L21/8221H01L21/823842H01L27/0688H01L27/092H01L29/78696H01L29/42392B82Y10/00H01L29/66439
Inventor 戈立新陆叶J·J·朱
Owner QUALCOMM INC