Display panel and pixel circuit thereof

A pixel circuit and display panel technology, applied to static indicators, instruments, etc., can solve the problems of signal voltage conversion and loading, affecting optical effects, etc.

Pending Publication Date: 2022-03-01
AU OPTRONICS CORP
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AI-Extracted Technical Summary

Problems solved by technology

For example, current division affects optical effects, si...
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Abstract

The invention provides a pixel circuit and a display panel. The pixel circuit comprises a driving unit, a light-emitting element and a light-emitting control circuit which are connected in series between a power supply voltage and a reference power supply; the first driving block is coupled to a control end of the driving unit and a vertical signal line, and is used for outputting a control signal to the driving unit according to a pulse width modulation signal and an amplitude modulation signal, and receiving a reference voltage from the vertical signal line at a light emitting time, receiving the pulse width modulation signal from the vertical signal line at a data writing time; and the second driving block is connected to the vertical signal line and is used for outputting the reference voltage to the first driving block through the vertical signal line at the light emitting time. The data writing time and the light emitting time form a frame.

Application Domain

Static indicating devices

Technology Topic

Voltage referencePulse width modulated +5

Image

  • Display panel and pixel circuit thereof
  • Display panel and pixel circuit thereof
  • Display panel and pixel circuit thereof

Examples

  • Experimental program(1)

Example Embodiment

[0028] Below in conjunction with accompanying drawing, structure principle and working principle of the present invention are described in detail:
[0029] Please refer to figure 1 , figure 1 It is a block diagram of a pixel circuit according to an embodiment of the present invention. The pixel circuit 100 includes a driving unit 120 , a light-emitting controller 130 , a light-emitting element LED, a first driving block 150 and a second driving block 160 .
[0030] The driving unit 120 includes a driving transistor TD. The driving transistor TD has a control terminal for receiving a control signal CS, wherein the control signal CS may include a pulse width control signal and an amplitude control signal. The driving transistor TD generates a driving signal according to the control signal CS to drive the light-emitting element LED to emit light. In this embodiment, the light emitting element LED can be any form of light emitting diode.
[0031] The circuits 130-1 and 130-2 in the lighting controller 130 are coupled in series with the driving transistor TD and the light-emitting element LED. The driving transistor TD is coupled between the circuits 130-1 and 130-2. In this embodiment, the circuits 130-1 and 130-2 respectively include transistors T1 and T2, and are coupled between the driving transistor TD, the power supply voltage VDD and the light-emitting element LED. The control terminals of the transistors T1 and T2 respectively receive a first lighting control signal EM1 and a second lighting control signal EM2, and are turned on or off according to the first lighting control signal EM1 and the second lighting control signal EM2 respectively. It should be noted that, in alternative embodiments, the circuits 130-1 and 130-2 in the lighting controller 130 may be implemented alternatively, and it is not necessary to provide the circuits 130-1 and 130-2 at the same time.
[0032] The first driving block 150 is used for generating the control signal CS according to the pulse width modulation signal D_PWM and the amplitude modulation signal D_PAM. The first driving block 150 is coupled to a vertical signal line VL. During a data writing period of a frame, the first driving block 150 receives the pulse width modulation signal D_PWM through the vertical signal line VL; The driving block 150 receives a reference voltage PPO through the vertical signal line VL.
[0033] The second driving block 160 is coupled to the first driving block through vertical signal lines. During the light-emitting time, the second driving block 160 outputs the reference voltage PPO.
[0034] In one embodiment, the light-emitting controller 130 controls the light-emitting element LED to emit light intermittently at least twice during the light-emitting time.
[0035] Please refer to figure 2 , figure 2 It is a block diagram of a display panel according to an embodiment of the present invention. The display panel 200 includes a plurality of pixel circuits P11 -Pxy, a plurality of horizontal signal lines HL1 -HLx, a plurality of vertical signal lines VL1 -VLy, and a control chip 210 . The pixel circuits P11 to Pxy can be implemented using the pixel circuit 100 . The pixel circuits P11 to Pxy are arranged in x rows and y columns, where x and y are positive integers. Each row of pixel circuits is coupled to the control chip 210 through corresponding horizontal signal lines. The pixel circuits of each column are coupled to the control chip 210 through corresponding vertical signal lines. The pixel circuits are further divided into at least two groups, and this embodiment takes two groups as an example. The pixel circuits of the first group and the second group respectively include multiple rows of pixel circuits, wherein the pixel circuit row belonging to the first group is called the first pixel circuit row, and the pixel circuit row belonging to the second group is called the second pixel circuit row. In one embodiment, the first pixel circuit row and the second pixel circuit row are arranged alternately. For example, pixel circuits of odd-numbered rows are assigned to the first group, and pixel circuits of even-numbered rows are assigned to the second group. The first group of pixel circuits operates at a first timing, and the second group of pixel circuits operates at a second timing, wherein the start of the first timing and the start of the second timing have a time difference.
[0036] with the following image 3 The details of the invention are illustrated for a circuit diagram of a pixel circuit according to an embodiment of the invention.
[0037] The pixel circuit 300 includes a driving transistor TD, transistors T1-T8, a light-emitting element LED, and capacitors C1 and C2. The pixel circuit 300 belongs to the pixel circuit of the nth row and the mth column of the display panel 200 , wherein n is a positive integer not greater than x, and m is a positive integer not greater than y. In this embodiment, the driving transistors TD, T1-T8 are all PMOS.
[0038] The first terminal of the transistor T1 receives the power supply voltage VDD. The control terminal of the transistor T1 receives the first lighting control signal EM1[n]. The first terminal of the driving transistor TD is coupled to the second terminal of the transistor T1. The first terminal of the transistor T2 is coupled to the second terminal of the driving transistor TD. The control terminal of the transistor T2 receives the second light emission control signal EM2[n]. The first terminal of the light-emitting element LED is coupled to the second terminal of the transistor T2. The second end of the light-emitting element LED receives the reference power VSS. The first terminal of the transistor T3 is coupled to the first terminal of the driving transistor TD. The control terminal of the transistor T3 receives a first gate driving signal G1[n]. The second terminal of the transistor T3 receives the amplitude modulation signal D_PAM[m]. The first terminal of the transistor T4 is coupled to the control terminal of the driving transistor TD. The control terminal of the transistor T4 receives the first gate driving signal G1[n]. The first terminal of the transistor T5 is coupled to the first terminal of the transistor T4. The control terminal of the transistor T5 is coupled to the second terminal of the transistor T4. The second end of the transistor T5 is connected to the corresponding vertical signal line VL. The first terminal of the transistor T6 is coupled to the second terminal of the driving transistor TD. The second terminal of the transistor T6 is connected to the first terminal of the transistor T4. The control terminal of the transistor T6 receives a second gate driving signal G2[n]. The first terminal of the transistor T7 is coupled to the second terminal of the transistor T6. The second terminal of the transistor T7 receives a reset voltage RES. The control terminal of the transistor T7 receives a reset control signal RES[n]. The first end of the transistor T8 is connected to the corresponding vertical signal line VL. The second terminal of the transistor T8 receives the reference voltage PPO. The signal received by the control terminal of the transistor T8 is determined according to the group to which the pixel circuit 300 belongs. When the pixel circuit 300 belongs to the first group, the signal is the first switching signal IF1, and when the pixel circuit 300 belongs to the second group, the signal is The second switching signal IF2. The first switching signal IF1 and the second switching signal IF2 are configured such that the data writing time and light-emitting time corresponding to the first group of pixel circuits and the data writing time and light-emitting time corresponding to the second group of pixel circuits have the same value. Time difference. The first terminal of the capacitor C1 receives the power supply voltage VDD. The second terminal of the capacitor C1 is coupled to the first terminal of the transistor T4. The first terminal of the capacitor C2 is coupled to the second terminal of the transistor T4. The second end of the capacitor C2 receives the time-dependent control signal SWEEP[n].
[0039] In this embodiment, the lighting controller includes transistors T1 and T2. The first driving block includes transistors T1-T7 and capacitors C1 and C2. The second driving block includes transistor T8.
[0040]The first gate driving signal G1[n], the second gate driving signal G2[n], the first emission control signal EM1[n], the second emission control signal EM2[n], the reset signal RES[n], The time control signals SWEEP[n] are all signals corresponding to the pixel circuits in the nth row, and can be generated by a gate on array (GOA), wherein the GOA circuit can be integrated in the control chip or partially integrated in the control chip to Extra settings. The first switching signal IF1 and the second switching signal IF2 can be generated by the control chip. The pulse width modulation signal D_PWM[m] and the amplitude modulation signal D_PAM[m] are data corresponding to the pixel circuit of the mth column, and can be generated by the control chip. In one embodiment, the m-th vertical signal line can be coupled to the control chip through a multiplexing circuit MXm. The multiplexing circuit MXm selectively outputs the reference voltage PPO and the pulse width modulation signal D_PWM according to the first switching signal IF1 (or the second switching signal IF2, depending on whether n is odd or even) and the multiplexing control signal MXCS. In one embodiment, the multiplexing circuit MXm may include transistors T9 and T10. The first terminal of the transistor T9 receives the reference voltage PPO. The second end of the transistor T9 is connected to the vertical signal line VLm. The control terminal of the transistor T9 receives the first switching signal IF1 (or the second switching signal IF2). The first terminal of the transistor T10 receives the pulse width modulation signal D_PWM[m]. The second end of the transistor T10 is connected to the vertical signal line VLm. The transistor T10 receives the multiplexing control signal MXCS.
[0041] Specifically, during the data writing time, the first switching signal IF1 and the second switching signal IF2 cause the transistors T8 and T9 to be turned off, and the multiplexing control signal MXCS causes the transistor T10 to be turned on; during the light-emitting time, the first switching signal IF1 And the second switching signal IF2 causes the transistors T8 and T9 to be turned on, and the multiplexing control signal MXCS causes the transistor T10 to be turned off.
[0042] Please refer to Figure 4 , Figure 4 It is a schematic diagram of the operation and signal timing of the display panel. 400 is a schematic diagram of the operation of the first group of pixel circuits, and 410 is a schematic diagram of the signal timing used by the first group of pixel circuits. In 400, the horizontal axis is time, and the vertical axis is the number of the first pixel circuit row, such as 1, 3, 5, . . . from bottom to top. One frame FR1 is divided into a data writing time t1 and a light emission time t2. At the data writing time t1, the first switching signal IF1 maintains a high potential, and after clearing the old pixel data in the pixel circuit, new pixel data is written according to the pulse width modulation signal and the amplitude modulation signal. At the light-emitting time t2, the first switching signal IF1 is at a low potential, and the first pixel circuit row emits light intermittently row by row. In this embodiment, the interval of intermittent light emission is a quarter of the length of the frame FR1, namely (t1+t2)/4. 420 is a schematic diagram of the operation of the second group of pixel circuits, and 430 is used by the first group of pixel circuits Schematic diagram of the signal timing. In 420, the horizontal axis is time, and the vertical axis is the number of the second pixel circuit row, such as 2, 4, 6, . . . from bottom to top. Similarly, one frame FR2 is divided into a data writing time t1 and a light emission time t2. At the data writing time t1, the second switching signal IF2 maintains a high potential, and after clearing the old pixel data in the pixel circuit, new pixel data is written according to the pulse width modulation signal and the amplitude modulation signal. At the light-emitting time t2, the second switching signal IF2 is at a low level, and the second pixel circuit row emits light intermittently row by row. In this embodiment, the interval of intermittent light emission is a quarter of the length of the frame FR2, that is, (t1+t2)/4. It should be noted that there is a time difference t3 between the start time of the frame FR2 and the start time of the frame FR1. In this embodiment, the lengths of the frames FR1 and FR2 are the same, which are both t1+t2, and the time difference t3 is half the length of the frames FR1/FR2, that is, t3=(t1+t2)/2.
[0043] To be more specific, each group of pixel circuits uses sequential scanning to emit light, and the multiple groups of pixel circuits use interlace to emit light. By overlapping 400 and 420, it can be seen that the pixel circuits of the first group and the second group are equivalent to emit light four times in total in one frame. And the four times of light emission evenly divide the time of one frame. If the length of a frame is 16.6ms, an update rate of 60Hz can be achieved. That is to say, the desired update rate can be determined by appropriately configuring the number of groups of pixel circuits grouped and the number of times each group of pixel circuits emits light within a frame time. For example, the pixel circuits can be divided into three groups, and each group of pixel circuits emits light three times in the light-emitting time, which is equivalent to uniformly light-emitting nine times in one frame time.
[0044] Please refer to Figure 5 , Figure 5 It is a circuit diagram of a pixel circuit according to another embodiment of the present invention. The pixel circuit 500 includes a driving transistor TD, transistors T1-T15, a light-emitting element LED, and capacitors C1-C3.
[0045] The first terminal of the transistor T1 is coupled to the first terminal of the driving transistor TD. The first terminal of the transistor T2 is coupled to the second terminal of the driving transistor TD. The control terminal of the transistor T2 receives the light emission control signal EM_PAM[n]. The first terminal of the light-emitting element LED is coupled to the second terminal of the transistor T2. The second end of the light-emitting element LED receives the reference power VSS. The first terminal of the transistor T3 receives the amplitude modulation signal D_PAM[m]. The second terminal of the transistor T3 is coupled to the second terminal of the transistor T1. The control terminal of the transistor T3 receives the gate driving signal G2[n]. The first terminal of the transistor T4 is coupled to the second terminal of the transistor T3. The control terminal of the transistor T4 receives the lighting control signal EM_PWM[n]. The second end of the transistor T4 is coupled to the power supply voltage VDD. The first terminal of the transistor T5 is coupled to the second terminal of the transistor T4. The control terminal of the transistor T5 is coupled to the control terminal of the transistor T4. The first terminal of the transistor T6 is coupled to the second terminal of the transistor T5. The control terminal of the transistor T6 receives the set signal VST[n]. The second terminal of the transistor T6 receives the reference voltage PPO. The first terminal of the transistor T7 is coupled to the second terminal of the transistor T5. The second terminal of the transistor T7 is coupled to the second terminal of the transistor T6. The control terminal of the transistor T7 receives the gate driving signal GATE[n]. The first terminal of the transistor T8 is coupled to the first terminal of the transistor T1. The second terminal of the transistor T8 is coupled to the control terminal of the transistor T1. The control terminal of the transistor T8 is coupled to the control terminal of the transistor T3. The first terminal of the transistor T9 is coupled to the second terminal of the transistor T8. The control terminal of the transistor T9 receives the signal VST[n]. The second terminal of the transistor T9 is coupled to the control terminal of the transistor T9. The first terminal of the transistor T10 is coupled to the control terminal of the driving transistor TD. The control terminal of the transistor T10 receives the light-emitting control signal EM_PWM[n]. The first terminal of the transistor T11 is coupled to the second terminal of the transistor T10. The control terminal of the transistor T11 receives the set signal SET[n]. The second terminal of the transistor T11 receives the set voltage VSET. The first end of the transistor T12 is coupled to the first end of the transistor T11. The control terminal of the transistor T12 is coupled to the control terminal of the transistor T7. The first terminal of the transistor T13 is coupled to the second terminal of the transistor T12. The second terminal and the control terminal of the transistor T13 are coupled to the second terminal of the transistor T9. The first terminal of the transistor T14 is coupled to the first terminal of the transistor T12. The second end of the transistor T14 is connected to the vertical signal line VLm, and receives the pulse width modulation signal D_PWM[m] at the data writing time through the vertical signal line VLm. The control terminal of the transistor T14 is coupled to the second terminal of the transistor T12. The first end of the transistor T15 is connected to the vertical signal line VLm. The second terminal of the transistor T15 receives the reference voltage PPO. The control terminal of the transistor T15 receives the switching signal IF. The first terminal of the capacitor C1 is coupled to the second terminal of the transistor T12. The second end of the capacitor C1 receives the time control signal SWEEP[n]. The first terminal of the capacitor C2 is coupled to the control terminal of the transistor T1. The second terminal of the capacitor C2 is coupled to the second terminal of the transistor T5. The first terminal of the capacitor C3 is coupled to the first terminal of the transistor T10. The second terminal of the capacitor C3 is coupled to the second terminal of the transistor T11.
[0046] In this embodiment, the transistor T1 is also configured as a transistor for driving the light emitting element LED. The control terminal of the driving transistor TD receives the pulse width control signal generated according to the pulse width modulation signal D_PWM[m]. The control terminal of the transistor T1 receives the amplitude control signal generated according to the amplitude modulation signal D_PAM[m]. That is to say, in this embodiment, the driving unit includes a driving transistor TD and a transistor T1, and the first driving block includes a circuit for generating a pulse width control signal and outputting it to the control terminal of the driving transistor TD and a circuit for generating an amplitude control signal A circuit that outputs the signal to the control terminal of the transistor T1. The second driving block is the transistor T15.
[0047] have to be aware of is, image 3 The 8T2C (Eight Transistor Two Capacitor) architecture with Figure 5 The 16T3C (16-transistor, 3-capacitor) architecture shown above is just an example, and any suitable PWM/PAM driving circuit architecture can be applied to the present invention.
[0048] The advantage of the present invention is that the vertical signal lines and the second driving block can provide a stable reference voltage PPO to the first driving block (PAM/PWM driving circuit) during the light-emitting time without being pumped from the power supply voltage. This method can avoid visual flickering caused by unstable brightness caused by current shunt when emitting light.
[0049] Of course, the present invention can also have other various embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding Changes and deformations should belong to the protection scope of the appended claims of the present invention.

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