Semiconductor device
A semiconductor and device technology, applied in the field of semiconductor devices, can solve problems such as complex circuit patterns, parasitic capacitance and/or increased leakage current
Pending Publication Date: 2022-03-18
SAMSUNG ELECTRONICS CO LTD
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Problems solved by technology
[0004] As semiconductor devices become highly integrated, individual circuit patterns for realizing as many semiconductor devices as possible in any given area become more complex
[0005] Meanwhile, as the integration density of semiconductor memory devices increases, the influence of parasitic capacitance and / or leakage current gradually increases
Method used
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[0022] When the term "about" or "substantially" is used in connection with a numerical value in this specification, it is intended that the associated numerical value includes manufacturing or operating tolerances (eg, ±10%) around the stated value. Additionally, when the words "substantially" and "substantially" are used in conjunction with a geometric shape, the intent is that no precision of the geometric shape is required, but that the range of shapes is within the scope of the present disclosure. Furthermore, regardless of whether values or shapes are modified as "about" or "substantially," it should be understood that these values and shapes should be interpreted to include manufacturing or operating tolerances (e.g., ±10% ).
[0023] Expressions such as "at least one of," when preceding a list of elements (eg, A, B, and C), modify the entire list of elements and do not modify the individual elements of the list. For example, "at least one (species) of A, B, and C",...
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A semiconductor device may include a substrate including a trench and a contact recess, the contact recess having a curved surface profile; a conductive pattern in the trench; a buried contact including a first portion filling the contact recess and a second portion on the first portion; and a spacer structure including a first spacer and a second spacer. The second portion may be columnar and has a width less than a width of a top surface of the first portion. The buried contact may be spaced apart from the conductive pattern by a spacer structure. The first spacer may be on a first portion of the buried contact at an outermost portion of the spacer structure. The first spacer may extend along a second portion of the buried contact and contact the buried contact. The second spacer extends along a side surface of the conductive pattern and the trench. The second spacer may contact the conductive pattern. The first spacer may include silicon oxide.
Description
[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2020-0119799 filed on September 17, 2020, the disclosure of which is incorporated by reference in its entirety into this application. technical field [0003] The present disclosure relates to semiconductor devices. Background technique [0004] As semiconductor devices become highly integrated, the individual circuit patterns for realizing as many semiconductor devices as possible in any given area become more complex. [0005] Meanwhile, as the integration density of semiconductor memory devices increases, the influence of parasitic capacitance and / or leakage current gradually increases. Since the parasitic capacitance and leakage current degrade the operating characteristics of the semiconductor device, there is a need for semiconductor devices that can reduce and / or minimize the parasitic capacitance and leakage current. Contents of the inven...
Claims
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IPC IPC(8): H01L27/108
CPCH10B12/30H10B12/315H10B12/0335H10B12/482H10B12/03H10B12/488H10B12/34H10B12/485
Inventor 金真雅柳镐仁蔡教锡崔准容
Owner SAMSUNG ELECTRONICS CO LTD