Mixed bit width accelerator based on DSP and fusion calculation method

Abstract

According to the mixed bit width accelerator based on the high bit width DSP and the fusion calculation method, the DSP serves as a main calculation unit, a multiplier and a multiplicand are connected and shifted, namely different isolation bit widths are inserted, and multiple groups of arbitrary low bit width multiply-accumulate operation can be achieved. The accelerator supports any multiplication parallelism degree, and the DSP calculation performance is maximized; the method supports a multiplier and a multiplicand with any bit width, supports fixed and unfixed conditions of the multiplier, and is better in universality and wide in application range.

Description

technical field [0001] The invention relates to the design of a mixed-bit-width neural network accelerator, in particular to a mixed-bit-width accelerator based on a high-bit-width DSP and a fusion calculation method. Background technique [0002] The DSP mentioned in the present invention refers to the DSP IP in the FPGA, that is, the IP for realizing digital signal processing technology. The advantage of DSP lies in the high-speed and real-time nature of processing signals. There are special hardware multipliers inside the DSP, which can be used to quickly realize various digital signal processing algorithms. Taking the DSP48E1 IP of Xilinx 7 series FPGA as an example, it mainly includes a 25×18-bit wide multiplier, a 48-bit accumulator, etc., which can realize operations such as multiplication, multiplication accumulation, and bitwise logic operations without using FPGA resources. It is widely used in communication fields such as graphics and image processing, voice pro...

AI Technical Summary

Problems solved by technology

However, the existing problems are: 1) the neural network quantization bit width only considers 8 bits, and for networks with mixed bit width quantization, quantization parameters with lower bit width (such as 4 bit, 2 bit, 1 bit, etc.) are common; 2) only Consider the case of weight sharing, that is, the multipliers in the parallel two sets of multiplications are fixed, so the versatility is not strong; 3) limited by its 8-bit quantization bit width considerations, no higher degree of parallelism is proposed (i.e., realizing more sets at the same time) multiplication) implementation

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