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Hardware acceleration device and method, equipment and storage medium

A technology of hardware acceleration and storage media, which is applied to encryption devices with shift registers/memory, secure communication devices, electrical components, etc., which can solve the problem of large difference in computing time, unoptimized encryption and decryption speed, and unsatisfactory Requirements and other issues, to achieve the best effect of improving encryption and decryption speed and throughput

Pending Publication Date: 2022-03-25
SHENZHEN YILIAN INFORMATION SYST CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

like figure 1 In the prior art shown, the number of calculation rounds of SM4 encryption is 32, which is twice the number of round calculations of AES, the calculation time is quite different, the unit calculation speed is not balanced enough, and the encryption and decryption speed of the system is not optimal. unable to meet demand

Method used

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  • Hardware acceleration device and method, equipment and storage medium
  • Hardware acceleration device and method, equipment and storage medium
  • Hardware acceleration device and method, equipment and storage medium

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Embodiment Construction

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0031] It should be understood that when used in this specification and the appended claims, the terms "comprising" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude one or Presence or addition of multiple other features, integers, steps, operations, elements, components and / or collections thereof.

[0032] It should also be understood that the terminology used ...

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Abstract

The invention relates to a hardware acceleration device, method and equipment and a storage medium, and the device comprises SM4 encryption, AES128 encryption, AES192 encryption and AES256 encryption. Wherein SM4 encryption comprises an SM4 calculation unit 1 to an SM4 calculation unit 16, and 16 times of calculation are needed; the AES128 encryption needs 11 times of calculation, and the AES128 encryption comprises an AES calculation unit 1, an AES calculation unit 10 and an AES128 calculation unit 11; the AES 192 encryption needs 13 times of calculation, and comprises an AES calculation unit 1 to an AES calculation unit 12 and an AES 192 calculation unit 13; the AES 256 encryption needs 15 times of calculation, and comprises an AES calculation unit 1 to an AES calculation unit 14 and an AES 256 calculation unit 15. According to the method, four encryption modes are supported through integration and multiplexing, so that the encryption and decryption speed is greatly improved, and the throughput rate of the whole system is optimal.

Description

technical field [0001] The present invention relates to the technical field of hardware acceleration, in particular to hardware acceleration devices, methods, equipment and storage media. Background technique [0002] Encryption technology plays an important role in the field of information security. The symmetric encryption algorithm is currently the main algorithm used for information encryption because of its low computational cost, fast encryption speed, and high confidentiality. Such as figure 1 In the prior art shown, the number of calculation rounds of SM4 encryption is 32, which is twice the number of round calculations of AES, the calculation time is quite different, the unit calculation speed is not balanced enough, and the encryption and decryption speed of the system is not optimal. Unable to meet demand. Contents of the invention [0003] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a hardware acceleratio...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L9/08H04L9/06
CPCH04L9/0631H04L9/0863H04L2209/12H04L2209/125
Inventor 莫雄余桉汤晓东
Owner SHENZHEN YILIAN INFORMATION SYST CO LTD