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Time dependent line equalizer for data transmission system

A data clock and data technology, applied in the field of telecommunication systems, can solve the problems of reducing and achievable data rate, etc., and achieve the effect of low bit error rate and improved jitter tolerance

Pending Publication Date: 2022-06-24
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to practical limitations of the achievable clock accuracy, any given receiver sample may sample the equalized signal later or earlier than the specific point in time at which it is equalized, resulting in reduced BER, and due to the achievable clock The practical limit of accuracy and ultimately the maximum achievable data rate

Method used

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  • Time dependent line equalizer for data transmission system
  • Time dependent line equalizer for data transmission system
  • Time dependent line equalizer for data transmission system

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Embodiment Construction

[0045] Overview

[0046] In the following detailed description, numerous specific details are set forth by way of example in order to provide a thorough understanding of the relevant teachings. However, it will be apparent to those skilled in the art that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components and / or circuits have been described at a relatively high level without detail in order to avoid unnecessarily obscuring aspects of the present teachings.

[0047] As used herein, equalization refers to the removal of distortion caused by a signal transmitted through a channel. The teachings herein provide enhanced equalization systems and methods based on time-correlated equalization, wherein the time-correlation of the equalization is synchronized with the data transmission interval so that the equalizer can apply varying equalization within the transmission interval of each transmission symbol. With ...

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Abstract

A data equalization system includes a data clock input configured to receive a clock signal. There is an input node operative to receive a data signal of a transmission symbol that changes state in synchronization with a clock signal. There is a first tap coupled to the input node. The second tap is configured to receive a change in the data signal. At least one of the weight of the first tap or the weight of the second tap is modulated by a dynamic control parameter that is synchronously repeated with each transmission symbol.

Description

technical field [0001] The present invention relates generally to telecommunications systems, and more particularly to equalization in high rate data transmission systems. Background technique [0002] Modern electrical data transmission systems in networks and computing systems often use equalization techniques to reduce distortion caused by channel temporal dispersion and the resulting inter-symbol interference (ISI). In known systems, these equalization techniques are typically based on the use of feedforward equalization (FFE) in the transmitter and / or receiver equipment, combined with receiver continuous time equalization (CTE) and decision feedback equalization (DFE) in some systems. The goals of the equalization system include removing as much ISI as possible at the data sampling time in the receiver to improve the recoverable bit error rate (BER). As data rates in modern systems continue to rise to 100Gb / s and beyond, the achievable clock accuracy in practical imple...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L27/01
CPCH04L25/03038H04L25/03343H04L2025/03477H04L7/0008H04L7/0037H04L7/0058
Inventor T·比克马
Owner INT BUSINESS MASCH CORP