High-speed transceiver with adaptive equalization capacity

Abstract

The invention discloses a high-speed transceiver with an adaptive equalization capacity, comprising a transmitter and a receiver, wherein the receiver comprises an equalizer, a clock and data recovery circuit, a 8B / 10B decoder, a 8B / 10B error counter and an adaptive control logical module; the equalizer is used for receiving signals transmitted in a printed circuit board (PCB) circuit and generating equalizing signals; the clock and data recovery circuit is used for receiving the equalizing signals and detecting locking signals, and sending the locking signals to the adaptive control logical module; the 8B / 10B decoder is used for receiving signals transmitted by the clock and data recovery circuit and carrying out logical operation and error detection as well as generating error marks; the 8B / 10B error counter is used for receiving the error marks and accumulating the error rate; and the adaptive control logical module is used for combining the error rate with the locking signals and generating gain control signals for controlling the gain of the equalizer. The high-speed transceiver has the advantages of compensating transmission line loss, improving jitter tolerance, and reducing error rate of signal transmission.

Description

technical field [0001] The present invention relates to the technical field of high-speed transceivers, especially related to network equipment that uses improved digital control adaptive equalization to perform high-speed traffic reception and transmission, and automatically reduces transmission line loss with adjustable equalization levels and complies with dynamic changes in signal reception / transmission high-speed transceivers required. Background technique [0002] At present, high-speed transceiver (SERDES), as a signal conversion device, covers many fields such as communication, computer, industry and storage, and is usually used between chips and chips / modules or on backplanes / cables In systems that transmit large amounts of data. [0003] Furthermore, in data communication or switching fabric applications, high-speed transceiver configuration and system operation are the core links that determine the architecture. However, due to the conventional system configurati...

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Problems solved by technology

[0016] 1) The design of adaptive equalization circuit requires accurate analog circuit and device matching, which is difficult to meet the deep submicron integrated circuit design technology of high-speed transceivers;

[0017] 2) After the initial adjustment is completed, the transfer function curve rarely needs to be readjusted, and it is impossible to adjust it to match the transfer function of the line;

[0018] 3) Since the analog adaptive equalization circuit is connected to the signal path, the load on the high-speed data transmission line is increased. In the application, if you want to maintain the same performance, you need to have higher power, and the analog adaptive loop has been consuming power;

[0019] 4) The control algorithm is difficult to change according to different application environments

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