Spinning electronic device with narrow spin polarization layer
A technology of spin polarized layer and electron flow, which is applied in the direction of orthogonal magnetization magnetic head, magnetic head using thin film, data recording, etc., and can solve the problems affecting the life and reliability of the writing head
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example B
[0071] The spintronic device is formed to include a seed layer on the MP, MP notches formed on the seed layer, a spacer layer on the MP notches, SPL on the spacer layer, a cap layer on the SPL, a cover layer formed on the cover Top electrode on cap layer. The electron flow is supplied towards the main pole through the spintronic device. similar to Figure 4 of the spintronic device, the area A of the spacer layer-Mp interface of the spintronic device 1 Greater than the area A of the spacer layer-SPL interface 2 , where A 1 >A 2 . Since the device of Example B has the same layers as Example A except in a different order and thus a different shape, Example B illustrates the effect of spintronic device shape on switching characteristics without considering parasitic resistance effects.
example C
[0073] The spintronic device is formed to include a spacer layer on the MP, an SPL on the spacer layer, a cap layer on the SPL, and a top electrode. The electron flow is supplied towards the main pole through the spintronic device. Area A of the spacer layer-Mp interface of a spintronic device 1 Greater than the area A of the spacer layer-SPL interface 2 , where A 1 >A 2 .
[0074] Examples B-C show lower Vjump and higher spin torque efficiencies than Example A. Example C shows a lower Vjump and higher spin torque efficiency than Example B because the spintronic device of Example B includes a seed layer with parasitic resistance.
[0075] In one embodiment, the write head includes a main pole. The seed layer is over the main pole. A spin polarized layer (SPL) is located above the seed layer. The spacer layer is over the SPL. The rear shield is over the spacer layer. The spacer layer forms a first interface between the spacer layer and the back shield and a second int...
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