Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

High-speed encryption and decryption system and method for realizing MSI interrupt processing based on multi-algorithm IP core

An encryption and decryption, multi-algorithm technology, applied in the direction of electrical digital data processing, multi-programming devices, instruments, etc., to achieve the effect of improving efficiency, improving operation processing efficiency, and improving performance

Pending Publication Date: 2022-07-29
广州万协通信息技术有限公司
View PDF0 Cites 5 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] The purpose of the present invention is to provide a high-speed encryption and decryption system and method based on a multi-algorithm IP core to realize MSI interrupt processing, thereby solving the aforementioned problems in the prior art

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • High-speed encryption and decryption system and method for realizing MSI interrupt processing based on multi-algorithm IP core
  • High-speed encryption and decryption system and method for realizing MSI interrupt processing based on multi-algorithm IP core
  • High-speed encryption and decryption system and method for realizing MSI interrupt processing based on multi-algorithm IP core

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0059] The present embodiment provides a high-speed encryption and decryption system based on a multi-algorithm IP core to realize MSI interrupt processing, as shown in the figure, including a host computer and an encryption algorithm chip connected through a PCIe3.0 channel, and the encryption algorithm chip includes PCIe3.0. 0 core, DMA module, key controller, algorithm controller, multiple algorithm IP cores and their internal first storage units and second storage units, the DMA module provides multiple channels for encryption and decryption data transfer, the The algorithm controller receives the encryption and decryption commands issued by the host computer, and uses the algorithm IP core in the encryption and decryption commands to perform the encryption and decryption process operations. The first storage unit and the second storage unit inside the algorithm IP core cache the encryption and decryption source data. , the algorithm IP core performs encryption and decrypti...

Embodiment 2

[0071] This embodiment provides a high-speed encryption and decryption method for implementing MSI interrupt processing based on a multi-algorithm IP core, which is implemented based on the high-speed encryption and decryption system for implementing MSI interrupt processing based on a multi-algorithm IP core described in Embodiment 1, including: The following steps:

[0072] S1, configure the host computer, initialize the host computer, at this time all algorithm IP cores are in an idle state;

[0073] When the host computer completes the initialization, the driver software of the PCIe encryption and decryption chip in this design will read the Multiple Message Enable field in the MSI Message Control register of the PCIe3.0 core of the PCIe encryption and decryption chip from the MSI related registers of the PCIe configuration space, and obtain the The number of consecutive interrupts that can be used by the PCIe encryption and decryption chip is n, reads the MSI Message Data...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a high-speed encryption and decryption system and method for achieving MSI interrupt processing based on multi-algorithm IP cores, the system comprises an upper computer and an encryption algorithm chip connected through a PCIe3.0 channel, the encryption algorithm chip comprises the PCIe3.0 core, a DMA module, a secret key controller, an algorithm controller, a plurality of algorithm IP cores, a first storage unit and a second storage unit, and the first storage unit and the second storage unit are arranged in the algorithm IP cores; according to the system, under the application environment of the PCIe multi-algorithm IP core, the problems of insufficient interrupt vectors of the upper computer and MSI interrupt loss are solved. The number of MSI message interruptions sent by the PCIe encryption and decryption chip is reduced, the MSI interrupt processing load of an upper computer is reduced, the efficiency of processing MSI interruptions by a system is improved, the operation processing efficiency of multi-thread encryption and decryption is improved, and the performance of a PCIe encryption and decryption board card is greatly improved.

Description

technical field [0001] The invention relates to the technical field of computer encryption and decryption, in particular to a high-speed encryption and decryption system and method for implementing MSI interrupt processing based on a multi-algorithm IP core. Background technique [0002] PCIe has three interrupts, namely INTx interrupt, MSI interrupt, and MSI-X interrupt, of which INTx is optional (Legacy), and MSI / MSI-X must be implemented. [0003] INTx: A product of the PCI period, an interrupt mechanism adopted in order to be compatible with the four interrupt lines of INTA, INTB, INTC, and INTD of PCI. Since only four interrupts are supported and controlled by one state, this mechanism complicates software processing in multi-interrupt scenarios, especially in scenarios with nested interrupts. Many PCIe devices do not support this feature. [0004] The MSI interrupt mechanism supports up to 32 interrupt requests, and requires continuous interrupt vectors; [0005] MSI...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/60G06F13/40G06F13/28G06F9/48
CPCG06F21/602G06F13/28G06F13/4022G06F9/4812G06F2213/0026
Inventor 颜昕明何军王亮
Owner 广州万协通信息技术有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com