Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Fragment scheduling method based on WRR algorithm in graphics processor

A graphics processor and scheduling method technology, applied in the direction of processor architecture/configuration, image memory management, etc., can solve the problem of not having enough fragments, etc., and achieve the effect of balanced and reliable scheduling

Pending Publication Date: 2022-07-29
智绘微电子科技(南京)有限公司
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Although the above method can solve the first-in-first-out relationship between different scanning primitives and different channel scan fragments of the same primitive in actual processing, it prevents the fragments of subsequent primitives from being dyed in priority to the fragments of previous primitives. The raster module mainly scans Points, lines, and triangle primitives are mostly triangular primitives. Due to the characteristics of the triangle pyramid shape, the smaller the channel value in the figure, the fewer the number of segments scanned. On the contrary, if it is an inverted triangle, the channel value The larger the channel, the fewer the number of fragments scanned, and the gcu with a small number or the gcu with a large number is prone to not having enough fragments for staining

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Fragment scheduling method based on WRR algorithm in graphics processor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0018] It is easy to understand that, according to the technical solutions of the present invention, without changing the essential spirit of the present invention, those of ordinary skill in the art can propose various alternative structures and implementations. Therefore, the following specific embodiments and accompanying drawings are only exemplary descriptions of the technical solutions of the present invention, and should not be regarded as all of the present invention or as limitations or restrictions on the technical solutions of the present invention.

[0019] According to an embodiment of the present invention combined figure 1 A fragment scheduling method based on the WRR algorithm in a graphics processor is shown, including the following steps:

[0020] S1. Use the WRR algorithm to perform weight allocation ratios for multiple channels in the pixel scanning module;

[0021] S2. The scheduling module schedules the plurality of data fragments scanned by the pixel sc...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a fragment scheduling method based on a WRR algorithm in a graphics processor, which solves the problem of low dyeing balance of a fragment stainer, and adopts the main technical scheme that S1, weight matching is performed on a plurality of channels in a pixel scanning module through the WRR algorithm; s2, a scheduling module sequentially schedules a plurality of data fragments generated by scanning of a pixel scanning module to a fragment stainer according to the weights corresponding to the channels, scheduling is determined to be finished according to the fragment number corresponding to the weights or the empty state in the channels, and the fragment number is related to the processor number and the processor thread count in single fragment dyeing; s3, the scheduling module repeats the S2 until all the pixel scanning modules finish scheduling, and meanwhile, the fragment stainer id and the scheduling fragment number of each round corresponding to the finished scheduling are serially connected into a list; and S4, the scheduling module sequentially selects the fragment stainer with the minimum id to dye the scheduled fragments, reads the dyeing completion information of the fragment stainer according to the first-in first-out principle in the list in the step S3, and schedules the dyeing completion information to the pixel processing module again.

Description

technical field [0001] The present invention relates to the field of graphics processors, in particular to a segment scheduling method based on a WRR algorithm in a graphics processor. Background technique [0002] Fragment scheduling is a key technology in graphics processors and an important link in graphics processor performance improvement. [0003] At present, for example, a hardware-accelerated implementation method for dyeing fragment scheduling management in the Chinese invention patent GPU with publication number x, the raster in this patent is 8-channel pixel scanning, and every 2 channels are fixedly scheduled to 4 gcus, that is, 8 Channels correspond to 16 gcus. The patent mainly describes how 2 channels of raster are scheduled to 4 gcus, channel 0 is fixed to gcu0 and gcu2, and channel 1 is fixed to gcu1 and gcu3. [0004] Although the above method can solve the first-in-first-out relationship between different scanning primitives and different channel scanning...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06T1/20G06T1/60
CPCG06T1/20G06T1/60
Inventor 钱家祥石小刚
Owner 智绘微电子科技(南京)有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products