Device to realize Pascal's triangle numerical operation
A triangular and numerical technology, applied in the field of Pascal's triangular numerical calculation circuit, can solve the problems of complex serial circuits, increase product cost, and cannot satisfy the fast response of fractional frequency division circuits, etc., and achieve the effect of fast operation and simple circuit structure
Inactive Publication Date: 2004-05-05
SOUTHEAST UNIV
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Problems solved by technology
The programming look-up method needs to use the CPU, which is not practical in the N-fractional frequency division circuit
Although the speed of the serial circuit has been improved, it still cannot meet the fast response of the fractional frequency division circuit, and the serial circuit is very complicated, occupies a large area, and increases the cost of the product
Phase compensation and reduction of phase jitter of N-digital fractional frequency division output cannot be well realized
Method used
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Embodiment Construction
[0024] All the circuits of the present invention can be designed and integrated on an integrated circuit as a circuit module. It can also be composed of discrete components, such as:
[0025] D flip-flop D: model is CD4076; OR gate E: model is CD4071;
[0026] XOR gate F: model is CD4070; full adder circuit G: model is CD4008;
[0027] AND gate H: the model is CD4081;
[0028] The device for realizing Pascal's triangular numerical operation is composed of multi-stage accumulators connected in series to complete fast Pascal's triangular numerical operation in which the overflow of the multi-stage accumulator is input. Each level of accumulator is composed of delayer A, complementer B, and full adder C. The input terminal of delayer A is connected to the output terminal of the previous level of accumulator, and the output terminal of delayer A is connected to the full adder. The input terminal of the adder C, the input terminal of the full adder C is also connected with the o...
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The Pascal's triangle numerical operator is one for realizing N digital decimal frequency division output and with phase compensation and reduced phase tingle. The operator consists of several cascade accumulators, each of which comprises time delayer, complementor and full adder. The input terminal of the time delayer is connected to the output terminal of the forestage accumulator and output terminal connected to the input terminal of the accumulator; and input terminal of accumulator is connected to the output terminal of the complementor, the output terminal of the forestage accumulator and the signal input of the present stage. The time delayer consists of D trigger, the complementor of OR gate and XOR gate, and the full adder of adder circuit.
Description
technical field [0001] The invention is a Pascal triangle numerical operation circuit which realizes the phase compensation of the N-digit fractional frequency division output and reduces the phase shake. Background technique [0002] The increasing maturity of semiconductor technology and the needs of digital communication have promoted the gradual maturity of digital phase-locked loop technology, but people's requirements for phase-locked frequency are getting higher and higher, that is, they require fast capture function and high phase detection frequency. At the same time, ultra-fine resolution, good signal-to-noise ratio (S / N) and small phase jitter are required. For the single-loop frequency synthesizer, if the integer frequency divider is still used, it can no longer meet the needs of the application. In recent years, people generally use N-digital decimal frequency dividers for single-loop synthesizers. According to the requirements of the sy...
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IPC IPC(8): H03L7/16H03L7/18
Inventor 张嗣忠时龙兴陆生礼胡晨吴自信
Owner SOUTHEAST UNIV