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System and method for executing rearrangement instructions

A processor and executor technology, applied in the field of computer systems, which can solve problems such as the inability to support mobile rearrangement

Inactive Publication Date: 2004-07-21
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, according to processor implementations where less than 12 bits are available for the control register, full move rearrangement cannot be supported

Method used

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  • System and method for executing rearrangement instructions
  • System and method for executing rearrangement instructions
  • System and method for executing rearrangement instructions

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Embodiment Construction

[0092] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood by those of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the present invention.

[0093] The present invention provides a method of identifying the order of the data elements in the case where the number of bits available to the control register is less than the full number of bits. According to one aspect of the present invention, there is provided a method and apparatus for moving data elements in a packet operand (reorder operation). This rearrangement operation enables data of a certain scale to be rearranged into any combination of two source registers or memories or moved to a destination register. The destination regi...

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Abstract

An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.

Description

technical field [0001] The present invention generally relates to the field of computer systems, and more specifically relates to a device and method for realizing multi-dimensional calculation based on moving rearrangement operations. Background technique [0002] In order to improve the efficiency of multimedia applications and other applications with similar characteristics, a single instruction multiple data (SIMD) architecture has been implemented in computer systems to enable simultaneous operation of several data instead of one data with one instruction. In particular, the SIMD architecture has the advantage of combining many data elements within one register or memory location. Due to parallel hardware execution, multiple operations can be implemented in accordance with one instruction, thus significantly improving performance. [0003] Although many applications currently have the advantage of these operations in application, called pooling operations, there are st...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F9/315
CPCG06F9/30025G06F15/7885G06F9/30036G06F9/30032
Inventor P·鲁塞尔S·舍尼帕蒂M·克兰福特M·阿卜杜拉J·科凯K·贡
Owner INTEL CORP