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Circuit for setting up and detecting IDE period time in UDMA transmission mode

A cycle time and detection circuit technology, applied in the detection of faulty computer hardware, etc., can solve problems such as no automatic detection

Inactive Publication Date: 2004-12-15
MITAC INT CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When making settings, in principle, you should first understand and check whether the hard disks produced by each brand support UDMA transmission mode, and then set accordingly. However, in the traditional technology, this work can only be done manually. Query, or use known measuring instruments such as oscilloscopes or logic analyzers to measure the relevant signals of the IED interface, there is no automatic detection technology

Method used

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  • Circuit for setting up and detecting IDE period time in UDMA transmission mode
  • Circuit for setting up and detecting IDE period time in UDMA transmission mode
  • Circuit for setting up and detecting IDE period time in UDMA transmission mode

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Embodiment Construction

[0015] figure 1 It is a schematic diagram showing a computer system including an IDE interface. In this system architecture, the central processing unit 10 is connected to the main memory 11 through a system local bus 20 (Local Bus). The local bus 20 includes an address bus 21 , a data bus 22 , and a control bus 23 . The local bus 20 can be connected to a PCI or ISA bus 24 through a bridge 12 (Bridge).

[0016] The PCI / ISA bus 24 can be connected to a hard disk device 32 through an IDE interface 31 . The cycle detection device 4 of the present invention is connected to the IDE interface 31, and can automatically detect the cycle time of the IDE signal by detecting the relevant signal of the IDE interface 31, and then know the cycle time of the IDE interface 31 and the hard disk device. Whether the timing of UDMA mode has been set correctly.

[0017] figure 2 It is a block diagram showing the circuit function of the period detecting device 4 of the present invention. The ...

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Abstract

The invention relates to a circuit for measuring IDE cycle time at UDMA mode of transmission. The invented circuit includes a counting circuit, a control circuit for enabling the counting circuit, control circuit for inputting the counting, time clock signal source, buffer and display unit. The enabling control circuit generates an enabling signal to enable the counting circuit whose input end is connected to IDE interface. The control circuit for inputting the counting generates a signal for niputting the counting, in order to start and input the counting of the counting circuit whose input end is connected to IDE interface. Time clock signal source directly fetches from clock signal of PCI bus in the computer system or signal generator, which can generates high frequency time clock signal.

Description

technical field [0001] The present invention relates to a cycle time detection circuit, in particular to an automatic detection circuit for detecting an IDE (Interactive Use Data Exchange) cycle time set in UDMA (Ultra Direct Memory Access) transmission mode, based on Check if the UDMA transfer mode is set correctly in the IDE controller and hard drive. Background technique [0002] In a computer system, the connection between the host and peripheral devices is through an I / O interface. The communication interface between the hard disk and the host is from the earlier MFM (Multi-Function Memory or Module), ESDI (Enhanced Small / Standard Device Interface), IDE (Interactive Data Interchange), SCSI (Small Computer System Interface) to the newer regulations now. E-IDE (Enhanced-Interactive Data Exchange), ULTRA-DMA (Ultra-Direct Memory Access), FAST WIDE SCSI (Fast Wide Small Computer System Interface), ULTRASCSI (Ultra Small Computer System Interface), ULTRA WIDE SCSI ( Ultra-...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/22
Inventor 蔡俊男
Owner MITAC INT CORP