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Processor

A processor and data technology, applied in the field of processors that execute SIMD-type commands, can solve problems such as digital signal processing that takes a lot of time

Inactive Publication Date: 2006-03-22
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, in the SIMD operation of conventional processors, as described above, since the operands to be operated must be arranged in the same order, rearrangement of the operands is necessary, and there is a problem that digital signal processing takes a lot of time.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

example 1

[0788] mov r1,0x223;;mov

[0789] This command description indicates that only the command mov is executed.

example 2

[0791] mov r1,0x38

[0792] add r0,r1,r2

[0793] sub r3, r1, r2;

[0794] These command descriptions indicate that three commands mov, add, and sub are executed in parallel.

[0795] The command control unit 10 identifies the issued group and sends it to the decoding unit 20 . The decoding unit 20 analyzes the commands of the distribution group and controls necessary resources.

[0796] Next, the registers included in the processor 1 will be described.

[0797] The register set of the processor 1 is shown in Table 1 below.

[0798] Table 1

[0799] In addition, the flag groups (flags managed by condition flag registers and the like described later) of the present processor 1 are shown in Table 2 below.

[0800] Table 2

[0801] FIG. 8 is a diagram showing the structure of general-purpose registers (R0-R31) 30a. The general-purpose registers (R0-R31) 30a constitute part of the context (context) of the task to be executed, and are a group of 32-bit registers that store ...

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PUM

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Abstract

Provided is a processor capable of of executing flexible SIMD (single instruction multiple data) operation while minimizing the limitation related to the position of an operand that is the subject of the SIMD operation. This processor has a decode part 20, an operation part 40 and the like. When the decode part 20 decodes a command 'vxaddh Rc, Ra, Rb', a mathematic-logic / comparison computing unit 14 or the like performs (i) the addition of the high 16 bits of a register Ra to the low 16 bits of a register Rb and the storage of the result in the high 16 bits of a register Rc, and also performs, in parallel to this, (ii) the addition of the low 16 bits of the register Ra to the high 16 bits of the register Rb and the storage of the result to the low 16 bits of the register Rc.

Description

technical field [0001] The present invention relates to processors such as DSPs or CPUs, and more particularly to processors that execute SIMD-type instructions. Background technique [0002] Previously, as a processor supporting SIMD (Single Instruction Multiple Data: Single Instruction Multiple Data) type commands, there was MMX / SSE of Pentium(R) / Pentium(R)III / Pentium(R)4 of Intel Corporation of the United States. / SSE2 etc. [0003] For example, in the case of MMX, the same operation can be performed with one command for a maximum of 8 integers stored in a 64-bit MMX register. [0004] However, in the conventional processors described above, there is a problem that there are many constraints on the positions of operands (operands) that are objects of SIMD operations. [0005] For example, when the values ​​A and B are respectively stored in the upper and lower digits of the first register, and the values ​​C and D are respectively stored in the upper and lower digits of...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F9/302G06F9/305G06F9/38G06F15/80
CPCG06F9/30014G06F9/30018G06F9/30036G06F9/30145G06F9/30167G06F9/3885G06F9/3887G06F15/8015G06F9/30038G06F9/30
Inventor 田中哲也冈林羽月瓶子岳人小川一古贺义宏黑田学铃木正人清原督三田中健西田英志宫阪修二
Owner SOCIONEXT INC