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Dummy least recently used uniform replacement method of cache controller

A high-speed cache, the least recent technology, applied in the direction of memory system, instrument, memory address/allocation/relocation, etc., can solve the problem of no technical solution public report, etc., to reduce the running time of the program and reduce the number of Cache failures Effect

Inactive Publication Date: 2006-10-18
NAT UNIV OF DEFENSE TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0015] There is no public report of a technical solution to this type of problem

Method used

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  • Dummy least recently used uniform replacement method of cache controller
  • Dummy least recently used uniform replacement method of cache controller
  • Dummy least recently used uniform replacement method of cache controller

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Embodiment Construction

[0058] figure 1 It is a schematic diagram of a Cache with configurable size. You can configure all the memory as Cache, using four-way set associative; you can also configure three-quarters of the memory as Cache, using three-way set associative; you can also configure two-quarters of the memory as Cache, using two-way Way set associative; you can also configure a quarter of the memory as Cache, use one way set associative, and so on. The number of set associative caches is not fixed, but varies with the size of the configuration.

[0059] figure 2 It is a schematic diagram of a Cache structure under a four-way set associative in the background technology. The pseudo-LRU conversion control circuit controls the change of the LRU bit, and the LRU bit controls which data of W0, W1, W2, and W3 is replaced.

[0060] image 3 It is a schematic diagram of pseudo-LRU bit transformation state under 4-way set associative state in the background technology. The LRU bit can be any ...

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Abstract

The invention discloses an even replace method of pseudo cache latest least use. Technology problem needed to solve is overcoming disadvantage of uneven replace under circumstance that group linking channels are configurable and unfixed in orthodoxy replace method of LRU. It makes data of each channel can be evenly replaced in every configuration of maximum of linking groups is four or eight. When the maximum is four, three channels link is configured, while 3, 5, 6 and 7 channels is configured when the maximum is eight. Adopting the invention, uniformity problem of linking 3, 5, 6 and 7 channels group is solved and even replacement of each channel of data is guaranteed. And relative programs can be executed correctly. In some instance, times of cache invalidation and program running time can be reduced.

Description

technical field [0001] The present invention relates to the pseudo-least recently used (LeastRecent Used, abbreviated as LRU) uniform replacement method of a high-speed cache (Cache) controller with configurable capacity, especially the pseudo-LRU uniform replacement method of a Cache controller in a digital signal processor (DSP) . Background technique [0002] Driven by market demand, DSP chips are developing towards higher performance. More and more DSPs use Cache technology, and the performance has been greatly improved. For the convenience of users, the Cache of many DSPs is designed to be configurable in size, that is, the size of the Cache of the DSP can be changed as needed, and the part of the memory bank that is not configured as Cache is used as SRAM. In this case, the number of Cache set associativity is not fixed, but varies with the size of the configuration. [0003] The most commonly used replacement method in the Cache is the pseudo-LRU algorithm. Take th...

Claims

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Application Information

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IPC IPC(8): G06F12/12G06F12/123
Inventor 陈书明程由猛张丹瑜马鹏勇郭阳汪东孙书为胡定磊
Owner NAT UNIV OF DEFENSE TECH
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